Patents Represented by Attorney Turocy & Watson, LLP
  • Patent number: 8340678
    Abstract: Providing information related to a quality of a mobile communication link to an internal and/or external application provider is described herein. By way of example, a system can include component(s) that can receive communication link quality information associated with a mobile session, incorporate such information into a data packet, and forward such data packet to an application provider. The system can provide such information for second generation network components, third generation network components, and advanced components compatible with both second and third generation network architectures.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: December 25, 2012
    Assignee: AT&T Mobility II LLC
    Inventor: Vinod Pandey
  • Patent number: 8339830
    Abstract: According to one embodiment, a memory cell is configured using a field effect transistor and includes n anti-fuse elements, one ends of which are connected in common. A program voltage selection circuit selects, out of the n anti-fuse elements, an anti-fuse element to which a program voltage is applied. A sense amplifier is provided for the each memory cell and determines, based on data stored in the n anti-fuse elements, three or more values of readout levels.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Yamauchi, Daichi Kaku, Takehiko Hojo
  • Patent number: 8340711
    Abstract: Systems and methods are described that facilitate the provision of dual mode services. Access to the dual mode services is controlled by associating a mobile device to an access point. Subscribers are required to provide valid geographical addresses for access points associated with the mobile devices prior to provision of service. Consequently, physical addresses are necessarily available for emergency services (e.g., E911). Mobile devices are restricted to specific access points based upon the access point identifiers automatically provided during initialization of service and maintained for authorization purposes.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: December 25, 2012
    Assignee: AT&T Mobility II LLC
    Inventors: David Glass, Adnan Abu-Dayya
  • Patent number: 8339184
    Abstract: Systems, methods, and devices that generate a desired boosted gate voltage to facilitate controlling a charge pump are presented. A multi-phase charge pump (e.g., two-phase CMOS charge pump) can comprise a desired number of switch cells (SCs), wherein each SC can include a gate boost switch control component, which employs two transistors (without the need for external circuitry), and generates a desired gate voltage, based at least in part on a desired clock signal, wherein the desired gate voltage is applied to a charge transfer switch, Mc, of the SC to facilitate transferring a voltage across the Mc to a node on the other side of the Mc, in each stage of the charge pump, wherein the SCs are associated with a desired number of flying capacitors to facilitate increasing the input voltage to a desired output voltage.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: December 25, 2012
    Assignee: Canaan Microelectronics Corporation Limited
    Inventors: Chi Wah Kok, Oi Ying Wong, Wing Shan Tam
  • Patent number: 8338174
    Abstract: A material for ameliorating skin tissue provided by the invention comprises, as a main component, a culture obtained by culturing cells or tissue fragments derived from human or other mammalian alveolar mucosa. Typically, 50% or more of the cells contained in the culture are fibroblasts, and having a high growth rate and a high productivity in vascular endothelial cell growth factor (VEDF) and/or keratinocyte growth factor (KGF).
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: December 25, 2012
    Assignee: National University Corporation Nagoya University
    Inventors: Katsumi Ebisawa, Ryuji Kato, Hideaki Kagami, Minoru Ueda
  • Patent number: 8338911
    Abstract: In one embodiment, a semiconductor device including a substrate provided with a semiconductor element, and first and second interconnects provided above the substrate, each of the first and second interconnects having a line shape in a plan view, and the first and second interconnects being substantially parallel to each other. The device further includes a first via plug provided above the substrate, electrically connected to a lower surface of the first interconnect on a second interconnect side, and including a first recess part at an upper end of the first via plug under a first region between interconnects, the first region between interconnects being a region between the first interconnect and the second interconnect.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroko Miki, Makoto Wada, Yumi Hayashi
  • Patent number: 8338918
    Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Sekiguchi, Eiji Takano, Tatsuhiko Shirakawa, Kenichiro Hagiwara, Masayuki Dohi, Susumu Harada
  • Patent number: 8338908
    Abstract: According to one embodiment, a semiconductor device includes: a substrate in which, on a semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type and a semiconductor layer of the second conductivity type are stacked; trench that define an element forming region in the substrate; element isolation insulation film formed in the trench; and a semiconductor element formed in the element forming region. The trench include first trench formed from the surface of the substrate to boundary depth and second trench formed from the boundary depth to the bottom and having a diameter smaller than that of the first trench. First diffusion layers connected to the buried layer are formed around the first or second trench according to inter-element breakdown voltage required of the semiconductor element.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tetsuya Tsukihara
  • Patent number: 8336870
    Abstract: According to one embodiment, a separation and extraction apparatus includes an extraction unit, separation unit, air supply mechanism, detector, and controller. The extraction unit extracts and conveys one or more paper sheets from a stack of paper sheets. The separation unit separates one paper sheet from the other paper sheet(s) of the one or more paper sheets. The air supply mechanism supplies air toward a side surface of the stack. The detector detects a bundle state of the stack, which is related to a contact state between the paper sheets. The controller sets an extraction condition depending on the bundle state, which includes drive conditions for the extraction unit, separation unit, and air supply mechanism.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuko Kobayashi
  • Patent number: 8338859
    Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on said substrate, having two or more layers of composite layers in which a first semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the substrate and a second semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and smaller coefficient of thermal expansion than the first semiconductor layer are alternately laminated; a semiconductor operating layer comprising nitride based compound semiconductor formed on said buffer layer; a dislocation reducing layer comprising nitride based compound semiconductor, formed in a location between a location directly under said buffer layer and inner area of said semiconductor operating layer, and comprising a lower layer area and an upper layer area each having an uneven boundary surface, wherein threading dislocation extending from the lower layer area t
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: December 25, 2012
    Assignee: Furukawa Electric Co., Ltd
    Inventors: Takuya Kokawa, Sadahiro Kato, Yoshihiro Sato, Masayuki Iwami
  • Patent number: 8338904
    Abstract: According to an embodiment, there is provided a semiconductor device including a semiconductor substrate having a first surface on which an active layer having a light receiving portion is provided and a second surface to be a light receiving surface for the light receiving portion, a wiring layer provided on the active layer, an insulating layer provided to cover the wiring layer, and a supporting substrate joined to the semiconductor substrate via the insulating layer to face the first surface of the semiconductor substrate. A joined body of the semiconductor substrate and the supporting substrate includes an intercalated portion provided between its outer peripheral surface and the active surface. The intercalated portion is provided to penetrate the semiconductor substrate and the insulating layer from the second surface of the semiconductor substrate and to reach inside the supporting substrate.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Chiaki Takubo, Hideo Numata, Yoshihisa Imori
  • Patent number: 8338845
    Abstract: According to one embodiment, an LED package includes first and second lead frames, an LED chip and a resin body. The first and second lead frames are made of a metal material, and disposed to be apart from each other. The LED chip is provided above the first and second lead frames, the LED chip having one terminal connected to the first lead frame and another terminal connected to the second lead frame. The resin body is made of a resin material having a shore D hardness of 25 or higher. In addition, the resin body covers the first and second lead frames and the LED chip. And, an appearance of the resin body is an appearance of the LED package.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Gen Watari, Satoshi Shimizu, Hiroaki Oshio, Tatsuo Tonedachi, Kazuhisa Iwashita, Tetsuro Komatsu, Teruo Takeuchi
  • Patent number: 8340716
    Abstract: A wireless communication apparatus includes a first module, a second module, an inhibit module, a calculation module, and a control module. The first module constitutes a first system. The first system transmits and receives first data to and from a first device. The second module constitutes a second system. The second system transmits and receives second data to and from a second device in each interval time-divided with determined transmission timing. The inhibit module generates inhibit periods for preventing the first module from communicating by use of the first data. The calculation module calculates an occupation time required for the transmission and reception of the first data. The control module compares the period between the inhibit periods adjacent to one another with the occupation time and, according to the comparison result, instructs the first device to stop or delay the transmission of the first data.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Sekiya, Daisuke Taki
  • Patent number: 8339615
    Abstract: An edge detection method includes preparing a transparent substrate which includes a first main face having a first main region and a first peripheral region and a second main face having a second main region and a second peripheral region, the first peripheral region having an inclination angle of ?a1 and the second peripheral region having an inclination angle of ?a2, causing measuring light to enter the first peripheral region from a direction perpendicular to the first main region, detecting a non-emitting region where the measuring light is not emitted from the second peripheral region, and detecting an edge of the transparent substrate on the basis of the non-emitting region, wherein if a refractive index of the transparent substrate is n, the inclination angles ?a1 and ?a2satisfy the following expression: nĂ—sin(?a1+?a2?arcsin(sin ?a1/n))?1.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Dohi, Itsuko Sakai, Takayuki Sakai, Shunji Kikuchi, Takuto Inoue, Akihiro Hori, Masayuki Narita
  • Patent number: 8338895
    Abstract: A semiconductor device includes a first insulated-gate field-effect transistor which is disposed on a semiconductor substrate having an element formation plane in a (110) plane direction, and which has a channel length direction in a <?110> direction, a second insulated-gate field-effect transistor which is disposed on the semiconductor substrate, has a channel length direction in the <?110> direction, and neighbors the first insulated-gate field-effect transistor in the channel length direction, and a first liner insulation film which is provided in a manner to cover the first and second insulated-gate field-effect transistors, the first liner insulation film including a piezomaterial, having a positive expansion coefficient, and applying a compressive stress by operation heat to the first and second insulated-gate field-effect transistors in the channel length direction.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Zhengwu Jin
  • Patent number: 8341388
    Abstract: According to one embodiment, an information processing apparatus includes a display unit, a touch panel, a BIOS storage unit, and a setup program execution unit. The display unit displays various kinds of information. The touch panel is installed on a display screen of the display unit and used for input corresponding to a contact operation. The BIOS storage unit stores a BIOS (basic input/output system) to execute startup of an operating system. The setup program execution unit executes a setup program for the BIOS in response to that an input from the touch panel is detected during the execution of the startup based on the BIOS.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: December 25, 2012
    Assignee: Toshiba Tec Kabushiki Kaisha
    Inventor: Natsuko Fujii
  • Patent number: 8334914
    Abstract: Plural areas defined by contours in a through image (live view image) are previously set as object segments whose luminance levels are to be altered. When a user touches a point within an object segment seen in the through image displayed on a touch panel LCD 12, a gamma curve is changed to alter a luminance level of the object segment including the touched point. This arrangement allows the user to make more bright the whole of the object segment simply by touching a point within the object segment, and also to select any segment of an object as the object segment whose luminance level is to be altered.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: December 18, 2012
    Assignee: Casio Computer Co., Ltd
    Inventor: Kazunori Kita
  • Patent number: 8336101
    Abstract: Data communications between devices are selectively blocked and resurrected based on error notifications. Data communications from one or more source devices to one or more intended destination devices are selectively blocked based on content of the data communications. The blocked data communications are stored in a database. A blocked data communication is retrieved from the database in response to an error notification from one of the source devices and/or from one of the destination devices. The retrieved data communication is then sent to the intended destination device.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: December 18, 2012
    Assignee: Worcester Technologies LLC
    Inventors: Jeffrey A. Aaron, Jun-Gang Alin
  • Patent number: 8335725
    Abstract: Systems, methods, and apparatus for determining motivator counts associated with purchase selections are presented herein. A data store can be configured to store purchase selections of respective products. A server can be configured to determine an incremental purchase time between a first purchase selection of the purchase selections and a second purchase selection of the purchase selections. Further, the server can be configured to determine a standard deviation of incremental purchase times between respective purchase selections of the purchase selections. Furthermore, the server can be configured to increment a prime motivator count associated with the second purchase selection based on the incremental purchase time and the standard deviation.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: December 18, 2012
    Assignee: Meyer Cordless LLC
    Inventors: Richard C. Fuisz, Joseph M. Fuisz
  • Patent number: 8335680
    Abstract: An electronic apparatus comprises a display device, an input unit, a storage, and a processor. The processor accepts the input of a reading in the second language via the input unit, reads a kanji character in the second language corresponding to the input reading in the second language from the reading-kanji correspondence information stored in the storage, reads a kanji character in the first language corresponding to the read kanji character in the second language from the kanji correspondence information stored in the storage and performs display control of the read kanji character on the display device, and reads explanatory information that uses a character string including the kanji character in the first language subjected to display control as an entry word from dictionary information stored in the storage and performs display control of the explanatory information on the display device.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: December 18, 2012
    Assignee: Casio Computer Co., Ltd
    Inventor: Takuya Ako