Abstract: Disclosed are a silicon thin film anode for a lithium secondary battery having enhanced cycle characteristics and capacity and a preparation method thereof. A preparation method for a silicon thin film anode for a lithium secondary battery, comprises: preparing a collector including a metal; forming an anode active material layer including a silicon on the collector; forming one or more interface stabilizing layer, by annealing the collector and the anode active material layer under one of an inert atmosphere, a reduced atmosphere, and a vacuum atmosphere to react a metallic component of at least one of the collector and the anode active material layer with a silicon component of the anode active material layer at an interface therebetween; and forming a carbon coating layer on the anode active material layer by performing an annealing process in a hydrocarbon atmosphere.

Abstract: A memory card connector, within a slot of a host device, for receiving a first memory card having a first row of contact fingers and a second row of contact fingers and a second memory card having only a single row of contact fingers. The memory card connector includes a first row of contact pins, a second row of contact pins and a protrusion. The first row of contact pins are configured to mate with the first row of contact fingers of the first memory card. The second row of contact pins are configured to mate with the second row of contact fingers of the first memory card. The protrusion is received within a contact finger in the second row of contact fingers of the first memory card to allow full insertion of the first memory card into the connector, and abuts against a distal end of one of the contact fingers of the second memory card to prevent full insertion of the second memory card into the connector.

Abstract: In a programming operation, selected storage elements on a selected word line are programmed while unselected storage elements on the selected word line are inhibited from programming by channel boosting. To provide a sufficient but not excessive level of boosting, the amount of boosting can be set based on a data state of the unselected storage element. A greater amount of boosting can be provided for a lower data state which represents a lower threshold voltage and hence is more vulnerable to program disturb. A common boosting scheme can be used for groups of multiple data states. The amount of boosting can be set by adjusting the timing and magnitude of voltages used for a channel pre-charge operation and for pass voltages which are applied to word lines. In one approach, stepped pass voltages on unselected word lines can be used to adjust boosting for channels with selected data states.

Abstract: Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.

Abstract: A method for creating NAND flash memory. Source implantations are performed at a first implantation angle to areas between stacked gate structures of a NAND string. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The source implantation can include n-type and p-type materials implanted under different angles, and the drain implantation can include n-type and p-type materials implanted under different angles. Or, the source implantation can include multiple n-type implantations under different angles, and the drain implantation can include multiple n-type implantations under different angles.

Abstract: A vent cap for a direct vent system. The cap may include a base plate and a semicircular outer housing secured to the base plate. A divider is coupled within the outer housing, with the divider forming in exhaust region and an inlet region. A heat shield is positioned within the semicircular outer housing in the outlet region. A direct vent pipe coupling is provided in the base plate and includes a first pipe having an outlet coupled to the divider.

Abstract: A system for commoditizing data center networking is disclosed. The system includes an interconnection topology for a data center having a plurality of servers and a plurality of nodes of a network in the data center through which data packets may be routed. The system uses a routing scheme where the routing is oblivious to the traffic pattern between nodes in the network, and wherein the interconnection topology contains a plurality of paths between one or more servers. The multipath routing may be Valiant load balancing. It disaggregates the function of load balancing into a group of regular servers, with the result that load balancing server hardware can be distributed amongst racks in the data center leading to greater agility and less fragmentation. The architecture creates a huge, flexible switching domain, supporting any server/any service, full mesh agility, and unregimented server capacity at low cost.

Abstract: A rule-based method of optimizing wire bonding jumps is disclosed which minimizes the amount of wire used for wire bonds and/or minimizes a number of power and ground pads on a substrate to support all wired connections.

Abstract: A memory card has a data scrambler that performs a data scrambling operation on data stored in the memory card according to a device ID associated with the memory card. The device ID is either set at the factory and permanently stored in the card, or configurable by a user or a host system.

Abstract: A method and system for programming and reading data with reduced read errors in a memory device. In one approach, date to be written to the memory device is scrambled using a first pseudo random number which is generated based on a page of the memory device to which the data is to be written, to provide first scrambled data, which is scrambled using a second pseudo random number which is generated based on a block of the memory device to which the data is to be written. This avoids bit line-to-bit line and block-to-block redundancies which can result in read errors. The data may also be scrambled using a third pseudo random number that depends on a section within a page. Scrambling may also be based on one or more previous pages which were written.

Abstract: In one aspect, lines in image data of an event are automatically found and repaired. For example, the event may be a sporting event which is played on a field, and the line segment is a field line on the field which may be obscured by a player, game ball or other object. The line segment is automatically detected in a mask image, and a portion of the line segment which is occluded by the object is automatically determined, and the object is automatically removed. The line segment can also be repaired. Optionally, a virtual viewpoint of the event is provided from the image, with the line repaired and the object removed. In another aspect, an object in an image of an event is automatically located by detecting blobs in the image which meet at least one specified criterion, such as size, aspect ratio, density or color profile.

Abstract: An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack.

Abstract: A process is performed periodically or in response to an error in order to dynamically and adaptively optimize read compare levels based on memory cell threshold voltage distribution. One embodiment of the process includes determining threshold voltage distribution data for a population of non-volatile storage elements, smoothing the threshold voltage distribution data using a weighting function to create an interim set of data, determining a derivative of the interim set of data, and identifying and storing negative to positive zero crossings of the derivative as read compare points.

Abstract: A storage system and method for operating the storage system that uses reversible resistance-switching elements is described. Techniques are disclosed herein for varying programming conditions to account for different resistances that memory cells have. These techniques can program memory cells in fewer attempts, which can save time and/or power. Techniques are disclosed herein for achieving a high programming bandwidth while reducing the worst case current and/or power consumption. In one embodiment, a page mapping scheme is provided that programs multiple memory cells in parallel in a way that reduces the worst case current and/or power consumption.

Abstract: A system and method for identifying a pointing organ or a pointing device in a field of imaging of a 3-D imaging system and for calculating a line of pointing relative to this organ or device are disclosed. The method and system may be used to enable a user to communicate with computer programs, such as computer games, 3-D design programs and the like. The method and system may further employ a trigger-like mechanism to identify a movement of a user that may be interpreted as trigger activation.

Abstract: Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components.

Abstract: An apparatus for highly controlled color composition and distribution within the face mix of semi-dry concrete mix paving stones.

Abstract: Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.

Abstract: High density semiconductor devices and methods of fabricating the same are disclosed. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which may be smaller than the smallest lithographically resolvable element size of the process being used. A first set of spacers may be processed to provide planar and parallel sidewalls. A second set of spacers may be formed on planar and parallel sidewalls of the first set of spacers. The second set of spacers serve as a mask to form one or more circuit elements in a layer beneath the second set of spacers. The steps according to embodiments of the invention allow a recursive spacer technique to be used which results in robust, evenly spaced, spacers to be formed and used as masks for the circuit elements.

Abstract: An anchor member securing system includes a securing member and a rebar cage structure secured to the member. The securing system may include at least a first foundation placement guide. The anchor members may comprise mudsill anchors and anchor bolts, and the system provides more exact placement of the member or members in a foundation.