Patents Represented by Attorney Volentine Francos, PLLC
  • Patent number: 6794297
    Abstract: To determine an optimum addition ratio of ethyl alcohol in the etching gas in a plasma etching unit, an ethyl alcohol addition ratio at which the isotropic etching rate of the etching mask is obtained, and on the basis of the obtained ethyl alcohol addition ratio, the optimum addition ratio is determined, by performing an etching process using an etching gas containing ethyl alcohol in the optimum addition ratio, the portions of the bottom antireflective coating which are not covered with the etching mask are removed. Thus, it is possible to provide a novel etching method capable of appropriately removing unnecessary portions of the bottom antireflective coating which are not covered by photoresist without causing much damage to the photoresist used as the etching mask.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: September 21, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Shuichi Noda
  • Patent number: 6794891
    Abstract: The control unit 21 takes in a test command and expected value data from input terminals 11 and 12 respectively, to output via an internal bus 30 the command to the function block 31 etc. and the expected value data to a decision unit 40. A processing result of the function block 31 etc. is provided to the decision unit 40, where it is compared to the expected value data in order to decide acceptability of the function block 31 etc. The decision result is held in an output unit 50 and output from an output terminal 104 etc. Such a configuration provides a semiconductor integrated circuit which can easily adjust the timing in a test operation mode and reduce the number of external terminals.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: September 21, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Takeshi Ichikawa
  • Patent number: 6795911
    Abstract: A computing device accesses multiple memory banks, which are selected by a bank selection instruction. The memory bank selected by the bank selection instruction is accessed by a memory access instruction immediately following the bank selection instruction. Following any instruction other than the bank selection instruction, a default memory bank is selected automatically. This scheme eliminates the need to select the default memory bank explicitly, and the need to save and restore the contents of a bank selection register when interrupts are served.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: September 21, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Tomomi Miyano
  • Patent number: 6790761
    Abstract: A semiconductor device having conductive paths separated by cavities is formed by depositing organic spin-on glass between the conductive paths, forming gaps between the organic spin-on glass and the conductive paths, and then removing the organic spin-on glass through the gaps. The gaps may be formed as a dummy pattern of via holes that are misaligned with the conductive paths, so that they extend past the upper surfaces of the conductive paths and form fine slits beside the conductive paths. This method of removing the spin-on glass leaves cavities that are free of unwanted oxide residue and debris, thereby minimizing the capacitive coupling between adjacent conductive paths.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: September 14, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Toyokazu Sakata
  • Patent number: 6790688
    Abstract: An improved method of high pass filtering a data set includes flattening the data set and then filtering the flattened data set with an adaptive filter. The data set is flattened by fitting it to a predetermined function, and then obtaining the difference between the original data set and the fitted data set. Beneficially, the predetermined function is a polynomial. The adaptive filter includes a masking function that has a constant, non-zero value (e.g., 1) within the bounds of the original data set and value of zero outside the bounds of the original data set.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: September 14, 2004
    Assignee: Wavefront Sciences Inc.
    Inventors: Thomas Daniel Raymond, Daniel Richard Hamrick, Daniel Ralph Neal
  • Patent number: 6791894
    Abstract: A power-source controller for reducing current consumption while a DRAM is in standby, includes a mode detection circuit inverting a disable signal having an L-level under the enable state and having an H-level under the disable state; an internal-power-source driver circuit having first and second transistors; and an internal-power-source reference circuit setting first and second driver control signals respectively to L-level and H-level when an L-level disable signal is input to turn on the first transistor and turn off the second transistor, supplying an external-power-source voltage as an internal-power-source voltage, setting the first driver control signal to H-level when an H-level disable signal is input, controlling the level of the second driver control signal to turn off the second transistor and control the first transistor, and supplying an internal power-source voltage lower than the external-power-source voltage.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: September 14, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Wataru Nagai, Akihiro Hirota, Junichi Suyama
  • Patent number: 6787892
    Abstract: In a semiconductor device including a semiconductor wafer having a main surface where a circuit element is formed, electrode pads are formed at an upper portion of the main surface of the semiconductor wafer as electrically connected with the circuit element. A sealing resin seals the upper portion of the main surface of the semiconductor wafer, and external connection terminals are formed at the upper portion of the main surface so as to project out from the surface of the sealing resin and are arrayed in a substantially regular pattern over specific intervals from one another. At least one of the external connection terminals has a shape different from the shape of the other external connection terminals. The shape of the external connection terminal is used as an index mark, so that the index mark forming process is simplified and the index mark does not come off.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: September 7, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yuuki Furuya, Akihisa Iguchi, Kentarou Arai
  • Patent number: 6787430
    Abstract: In a semiconductor device and method of manufacturing thereof, a semiconductor device having an SOI structure is provided with a capacitor including a first electrode in an SOI layer, a second electrode opposing the first electrode, and a dielectric film therebetween. An isolation region is provided as contained in the SOI layer to electrically isolate the first electrode from remaining areas of the SOI layer, such as active areas or the like. The method includes forming the isolation regions in the SOI layer, forming the first electrode in the SOI layer as electrically isolated from the remaining areas of the SOI layer by the isolation regions, forming the dielectric film on the first electrode, and forming the second electrode on the dielectric film opposite the first electrode.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: September 7, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Jun Kanamori
  • Patent number: 6787886
    Abstract: A semiconductor device includes a semiconductor substrate which has a major surface and a MOS transistor which has a gate and first and second diffusion regions and which is formed on the major surface. The semiconductor device also includes a laminated structure of a SOG layer, wherein the laminated structure is composed of a base layer and a surface layer formed on the base layer and is formed over the MOS transistor and wherein the surface layer is denser than the base layer.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: September 7, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Kazuhiko Asakawa, Wataru Shimizu
  • Patent number: 6787287
    Abstract: A photosensitive polymer of a resist composition includes a copolymer of alkyl vinyl ether containing silicon and maleic anhydride, represented by the following formula: where R1 is —H, —OSi(CH3)2C(CH3)3 or —OSi(CH3)3; R2 is —H, —OH, —OCOCH3, —OSi(CH3)2C(CH3)3 or —OSi(CH(CH3)2)3; R3 is —H, —OH or —OCOCH3; R4 is —H, —OSi(CH3)2C(CH3)3, —CH2OSi(CH3)2C(CH3)3 or —CH2OSi(CH(CH3)2)3; and at least one of R1, R2, R3 and R4 is a Si-containing group.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: September 7, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-woo Kim, Sang-gyun Woo, Yool Kang
  • Patent number: 6786970
    Abstract: A semiconductor fabricating device and method that minimize the influence of a process deteriorating material that is generated during first processes on second processes, when the plurality of processes are continually performed step by step. Operational failures are prevented during the course of the semiconductor fabricating processes, by directing air flow from a location where the second processes are carried out to a location where the first processes are carried out, to carry the process deteriorating gas away from the second processes. This reduces the frequency of failures during processing.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: September 7, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Don Oh, Tae-Sin Park
  • Patent number: 6787432
    Abstract: A semiconductor device includes a semiconductor substrate and an internal circuitry which is formed on the semiconductor substrate and which executes a predetermined operation. The device also includes a terminal which is connected to the internal circuitry and which receives an external signal and a protection circuitry which is formed on the semiconductor substrate. The protection circuitry includes a transistor having a first region of a first conductivity type, a second region of the first conductivity type and a third region of a second conductivity type. The first region is connected to the terminal. The second region is provided at a scribe line of the semiconductor substrate. The third region is defined by a region between the first region and the second region.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: September 7, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Shigeru Nagatomo
  • Patent number: 6787705
    Abstract: An interconnection structure comprises: an interlayer insulating film; and first interconnection layer to which low potential is applied and second interconnection layer to which high potential is applied when the interconnection structure is used, formed with the interlayer insulating film therebetween; and a via hole formed in the interlayer insulating film for electrically connecting the first interconnection layer and second interconnection layer. Overlap regions including regions of the first interconnection layer and the second interconnection layer faced said via hole are formed for both the first interconnection layer and second interconnection layer.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: September 7, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Eiichi Umemura
  • Patent number: 6785171
    Abstract: A semiconductor memory device includes a plurality of sub-wordlines, a plurality of sub-wordlines corresponding a redundancy main wordline, a plurality of redundancy memory cells each being coupled to each of the redundancy sub-wordlines, and a redundancy control circuit for disabling the main wordline selector when among the sub-wordlines, a sub-wordline to which a defective memory cell is coupled is addressed, and for controlling the sub-wordline to be replaced by the redundancy main wordline. The number of the redundancy sub-wordlines coupled to the redundancy main wordline is smaller than the number of the sub-wordlines coupled to the main wordline. Therefore, when among the sub-wordlines coupled to the main wordline, a sub-wordline to which a normal main memory cell is coupled is addressed, the main wordline selector is enabled to improve a redundancy flexibility and reduce a circuit area.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: August 31, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hi-Choon Lee, Byoung-Ju Kim
  • Patent number: 6784482
    Abstract: The nonvolatile semiconductor memory device includes a first conductivity-type semiconductor substrate where an active region is created, a floating gate which is formed on the first conductivity-type semiconductor substrate, and a control gate which is formed on the floating gate. A first conductivity-type high concentration diffused region is formed in the non-overlapping region of the floating gate in the active region.
    Type: Grant
    Filed: February 11, 2003
    Date of Patent: August 31, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Katsutoshi Saeki
  • Patent number: 6785172
    Abstract: In a semiconductor memory device according to the present invention, which allows a memory cell array unit and a memory circuit internal logic unit to be tested independently of each other, a first test circuit unit TCi1 to which an address signal a″, a scan-in signal SIN, a scan select signal SS and a shift clock signal SCLK are input, outputs an address signal a′″ and a scan-out signal SiOUT1. The address signal a′″ is input to the memory cell array unit MCA and a column selector CS, whereas the scan-out signal SiOUT1 is input to a second test circuit unit TCi2. The second test circuit unit TCi2, to which the scan-out signal SiOUT1, the scan select signal SS, a write control signal WCTRL and a scan clock signal SCLK are input, outputs at a scan-out signal SOUT. The first test circuit unit and the second test circuit unit each achieve a parallel/serial conversion function.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: August 31, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yoshiki Kobayashi
  • Patent number: 6780671
    Abstract: A semiconductor device includes a first wall and a second wall. The first wall is arranged in a pad region which surrounds a chip region, and the second wall is arranged on a semiconductor chip mounted in the chip region. Conductive lines are arranged between the first wall and the second wall and are encapsulated by an encapsulating material formed between the first and second walls.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: August 24, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Takashi Noguchi
  • Patent number: 6780725
    Abstract: A method of manufacturing vertical NPN and PNP transistors on a substrate includes forming a first oxide film, a P-polycrystal silicon film, and a second oxide film successively on N-silicon epitaxial film on the substrate. An opening is made in the first oxide film to expose the N-silicon epitaxial film and a bottom of the P-polycrystal silicon film anisotropically etching the second oxide film and the P-polycrystal silicon film, and then isotropically etching the exposed first oxide film. A part of the opening is plugged by growing a selective epitaxial layer including a P-monocrystal layer from the surface of the N-silicon epitaxial film, and growing a polycrystal layer from the bottom of the P-polycrystal silicon film. Then, within a PNP transistor section, position and impurity concentration of a P-N junction are adjusted by self-aligned implanting or diffusing of P-impurities into the N-silicon epitaxial layer through the opening.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: August 24, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hirokazu Fujimaki
  • Patent number: 6780697
    Abstract: A method of manufacturing an LDMOS transistor includes providing a semiconductor substrate of a first conductivity type having a well region of a second conductivity type formed on a surface of the substrate. Ions of the first conductivity type are implanted into a part of the well region with a predetermined energy. The substrate is subjected to a heat treatment so that the implanted ions are diffused to form a diffusion region of the first conductivity type on the surface of the substrate. Then, a gate oxide layer and a gate electrode are formed on the surface of the substrate. Finally, a drain region is formed on the surface of the substrate. The predetermined energy for the implantation is set so that an accelerated oxidation during a formation of the gate oxide layer is inhibited.
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: August 24, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Katsuhito Sasaki
  • Patent number: 6781862
    Abstract: To shorten the time of a test for detecting deteriorated capacitors, a semiconductor memory device having a 2T2C type memory cell structure is designed in such a way that a voltage VBL of a bit line pair which determines a voltage to be applied to ferroelectric memory cells and a voltage VPL of plate lines are so set as to satisfy a relationship of VBL=VPL<VDD where VDD is a supply voltage. This makes the size of the hysteresis loop of the ferroelectric capacitors smaller than that in case of VBL=VPL=VDD, a potential difference &Dgr;V between data “0” and data “1” can be made smaller than an operational margin of a sense amplifier. This makes it possible to detect a deteriorated ferroelectric capacitor without conducting a cycling test.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: August 24, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Kazuhiko Takahashi, Shinzo Sakuma, Shoichi Kokubo