Abstract: In a grid-tie inverter, the DC input is phase and pulse-width modulated to define multiple phase shifted voltage pulses with the width of each pulse being modulated according to the grid AC amplitude for the corresponding portion of the AC phase.

Abstract: In an ESD protection device making use of a LVTSCR structure, the holding voltage is increased by forming diodes in the p-well of the LVTSCR structure. This provides an alternative current path at high currents and provides a defined voltage drop thereby increasing the holding voltage.

Abstract: In an ESD protection circuit an NPN BJT snapback device is provided with high breakdown voltage by including a RESURF region or by forming a PIN diode in the BJT. Holding voltage is increased by forming a sub-collector sinker region with the desired configuration.

Abstract: In a dual direction BJT clamp, multiple emitter and base fingers are alternatingly connected to ground and pad and share a common sub-collector.

Abstract: In an analysis of a semiconductor device under test (DUT) using a Thermal Induced Voltage Alteration (TIVA) tool, the TIVA is connected to an output of the DUT and the DC component on the output is decoupled from the TIVA. The remaining AC component from the output is analyzed by the TIVA while scanning the DUT with a scanning laser to identify locations on the DUT that produce signal anomalies at the DUT output.

Abstract: In an I/O circuit, noise reduction and power savings are achieved by providing feedback from the output of the I/O driver to control the current through the pre-driver and thereby the current through the driver transistors after a non-zero time delay following a low to high or high to low data signal change.

Abstract: In a ESD protection device, hot carrier degradation and soft leakage are reduced by introducing a dynamic driver that includes a RC circuit for keeping the triggering circuit of the ESD device in an on-state for a certain period of time. This allows the current through the ESD protection device to be reduced during the RC delay time.

Abstract: In a non-volatile memory cell, a single poly SOI technology is used to save space and achieve low current programming by providing two capacitors formed in an n-material over an NBL, forming a inverter in an n-material over a PBL, and isolating the NBL from the PBL by means of a lightly doped region or a deep trench isolation region.

Abstract: In an NLDMOS, DMOS and NMOS device, the ability is provided for withstanding snapback conditions by providing one or more p+ emitter regions interdigitated between drain regions having drain contacts and electrically connecting the drain contacts to contacts of the emitter regions.

Abstract: In a programmable circuit making use of fuse cells, a snapback NMOS or NPN transistor or SCR without reversible snapback capability is used as an anti-fuse, and programming comprises biasing the control electrode of the transistor to cause the transistor to go into snapback mode.

Abstract: In an actively triggered ESD protection structure, the control electrode is triggered by an RC circuit, wherein the capacitor is a diffusion capacitor implemented as one or more forward or reverse biased p-n junctions.

Abstract: In an ESD protection circuit for an EEPROM erase pin a snapback device is provided for discharging high ESD currents, whereas the snapback device is operated in active mode during low voltage electrical overstress and to discharge post ESD event current by connecting an RC circuit over the control electrode of the snapback device. In order to handle high voltage normal operating conditions the snapback device is deactivated once VDD is applied by pulling the control electrode to ground using a VDD controlled switch.

Abstract: In a non-volatile memory cell, charge is stored in a fully isolated substrate or floating bulk that forms a storage capacitor with a first poly strip and includes a second poly strip defining a control gate and a third poly strip coupled to a read transistor gate.

Abstract: In an ESD device for fast switching applications based on a BSCR or NLDMOS-SCR, an anode junction control electrode is provided by not connecting the anode electrode to the collector of the BSCR or to the drain of the NLDMOS-SCR, and a cathode junction control electrode is provided by forming an additional n+ region in the BSCR or an additional p+ region in the p-well of the NLDMOS-SCR. The triggering voltage of the ESD device is adjusted after a time delay by controlling one or both of the control electrodes using an RC-timer-driver circuit.

Abstract: In an on-chip transformer, external electromagnetic field influences are reduced by providing an isolation transformer having primary and secondary windings with a figure 8 configuration so that current induced by an external magnetic field is nulled.

Abstract: In a SiGe BJT process, a diode is formed by defining a p-n junction between the BJT collector and BJT internal base, blocking the external gate regions of the BJT and doping the emitter poly of the BJT with the same dopant type as the internal base thereby using the emitter contact to define the contact to the internal base. Electrical contact to the collector is established through a sub-collector or by means of a second emitter poly and internal base both doped with the same dopant type as the collector.

Abstract: In an on chip battery and method of making an on-chip battery, the electrodes are formed from metal layers deposited as part of the chip fabrication process. An electrolyte is preferably introduced between the electrodes at time of packaging of the chip.

Abstract: In a method and structure for current balancing the emitter current in a multi-finger n-emitter of a BJT or BSCR, back-end or polysilicon resistors are applied between the emitter fingers and the power rail, with the resistors chosen to be larger the closer the emitter fingers are to the collector.

Abstract: In a non-volatile memory cell, charge is stored in a fully isolated substrate or floating bulk that forms a storage capacitor with a first poly strip and includes a second poly strip defining a read gate and a poly-filled trench defining a control gate.

Abstract: In a semiconductor device, a thin film resistor is formed by making use of an interconnect structure and etching back the layers over the glue layer of the interconnect structure and using the glue layer as a thin film resistor.