Patents Represented by Attorney W. James Brady, III
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Patent number: 7378293Abstract: A method for singulating a substrate such as a semiconductor wafer populated with a plurality of MEMS devices. A preferred embodiment of the present invention comprises mounting a glass cover onto the wafer, then orienting the wafer and removably mounting it on an adhesive tape. A partial cut or series of partial cuts is then made through the cover to facilitate the later removal of selected cover portions using an automated process. The dice are then separated using a series of full cuts made perpendicular and parallel to the partial cuts and the selected cover portions removed from each die. The separated dice are then packaged for use or for further fabrication.Type: GrantFiled: March 22, 2006Date of Patent: May 27, 2008Assignee: Texas Instruments IncorporatedInventor: Buu Quoc Diep
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Patent number: 7375873Abstract: Disclosed herein is method of operating a device that comprises an array of micromirrors. The method comprises a process usable for repairing stuck micromirrors of the micromirror array during the operation. The reparation process applies, at the ON state, two consecutive refresh voltages to the mirror plates of the micromirrors in the array with the pulses being separated in time longer than the characteristic oscillation time of the micromirrors. The reparation process can be applied independently to the micromirrors. Alternatively, the reparation process can be incorporated with a bias inversion process.Type: GrantFiled: February 28, 2005Date of Patent: May 20, 2008Assignee: Texas Instruments IncorporatedInventors: Satyadev Patel, James Dunphy, Peter Richards, Michel Combes
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Patent number: 7362530Abstract: An amplifier apparatus for use with a sensor includes: (a) a first and a second amplifying circuit segment coupled with the sensor and cooperating to effect substantially balanced handling of signals received from the sensor; the first amplifying circuit segment includes a first transistor device; the second amplifying circuit segment includes a second transistor device; (b) a countercurrent unit coupled with the first and second amplifying circuit segments for receiving a first indicator signal from the first transistor device and a second indicator signal from the second transistor device; the first indicator signal represents a first parameter in the first transistor device; the second indicator signal represents a second parameter in the second transistor device; the countercurrent unit provides feedback signals to at least one of the first transistor and second transistor devices to reduce input impedance of the apparatus.Type: GrantFiled: November 6, 2004Date of Patent: April 22, 2008Assignee: Texas Instruments IncorporatedInventor: Motomu Hashizume
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Patent number: 7362494Abstract: A method for making a micromirror device comprises is disclosed herein.Type: GrantFiled: April 12, 2007Date of Patent: April 22, 2008Assignee: Texas Instruments IncorporatedInventors: Andrew Huibers, Hongqin Shi, James C. Dunphy, Satyadev Patel
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Patent number: 7359813Abstract: Multiple parameters of manufactured units are continually measured until some of the units fail, where failure can be accelerated by adjusting operating conditions. Pre-failure data is then examined to find outliers or aberrant parameter values that may have contributed to the failures. The data is normalized to allow different parameters to be compared to one another. The parameters producing the highest outlier values are then used to screen subsequently manufactured units, thus significantly reducing the number of measurements that have to be taken to screen the units. Lower outlier values for these parameters are, however, used in screening subsequently manufactured units to “catch” potentially defective units.Type: GrantFiled: August 30, 2006Date of Patent: April 15, 2008Assignee: Texas Instruments IncorporatedInventor: Eric Wheeler Trant
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Patent number: 7355255Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.Type: GrantFiled: February 26, 2007Date of Patent: April 8, 2008Assignee: Texas Instruments IncorporatedInventors: Peijun J. Chen, Duofeng Yue, Amitabh Jain, Sue E. Crank, Thomas D. Bonifield, Homi C. Mogul
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Patent number: 7354853Abstract: The invention describes a method for the selective dry etching of tantalum and tantalum nitride films. Tantalum nitride layers (30) are often used in semiconductor manufacturing. The semiconductor substrate is exposed to a reducing plasma chemistry which passivates any exposed copper (40). The tantalum or tantalum nitride films are selectively removed using an oxidizing plasma chemistry.Type: GrantFiled: July 12, 2005Date of Patent: April 8, 2008Assignee: Texas Instruments IncorporatedInventors: Mona M. Eissa, Troy A. Yocum
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Patent number: 7354854Abstract: Nickel silicide contact regions are formed on a source (2), drain (3) and polycrystalline silicon gate (5) of an integrated circuit transistor by annealing it after a nickel layer has been deposited on the source, drain, and gate, with no cap layer on the nickel layer. Nickel silicide bridging between the gate and source and/or drain is avoided or eliminated by using a chrome etching process to remove un-reacted nickel and nickel remnants from exposed surfaces of dielectric spacers (6A,B) located between the gate and source and between the gate and drain. The chrome etching process includes use of a solution including cerric ammonium nitrate, nitric acid, and acetic acid.Type: GrantFiled: May 24, 2005Date of Patent: April 8, 2008Assignee: Texas Instruments IncorporatedInventor: Rajneesh Jaiswal
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Patent number: 7351632Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An oxide layer is formed in core and I/O regions of a semiconductor device (506). The oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A silicon nitride layer is grown (516) within PMOS regions of the core and I/O regions by a low temperature thermal process. Subsequently, an oxidation process is performed (518) that oxidizes the silicon nitride into silicon oxynitride.Type: GrantFiled: April 29, 2005Date of Patent: April 1, 2008Assignee: Texas Instruments IncorporatedInventors: Mark Robert Visokay, Luigi Colombo, James Joseph Chambers
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Patent number: 7348643Abstract: A semiconductor dual guardring arrangement is provided which is useful during electrostatic discharge (ESD) events as well as during normal operating conditions. In particular, an inner guard that is located closer to an active area provides desirable performance during normal operating conditions, while an outer guardring located further from the active area provides desirable performance during an ESD event.Type: GrantFiled: June 6, 2006Date of Patent: March 25, 2008Assignee: Texas Instruments IncorporatedInventors: Gianluca Boselli, Charvaka Duvvury
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Patent number: 7348228Abstract: A junction field effect transistor (JFET) is fashioned where a channel of transistor is buried deeply within the workpiece within which the JFET is formed. Burying the channel below the surface of the workpiece and/or away from overlying conductive materials distances a current that flows in the channel from outside influences, such as the effects of the overlying conductive materials. The deep channel also provides a more regular path for the current flowing therein by moving the channel away from non-uniformities on or near the surface of the workpiece, where said non-uniformities or irregularities would interrupt or otherwise disturb current flowing in a channel that is not as deep. These aspects of the deep channel serve to reduce noise and allow the transistor to operate in a more repeatable and predictable manner, among other things.Type: GrantFiled: May 25, 2006Date of Patent: March 25, 2008Assignee: Texas Instruments IncorporatedInventor: Xiaoju Wu
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Patent number: 7348265Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device (100), among other possible elements, includes a gate oxide (140) located over a substrate (110), and a silicided gate electrode (150) located over the gate oxide (140), wherein the silicided gate electrode (150) includes a first metal and a second metal.Type: GrantFiled: March 1, 2004Date of Patent: March 25, 2008Assignee: Texas Instruments IncorporatedInventor: Jiong-Ping Lu
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Patent number: 7348232Abstract: In accordance with the invention there is a method of forming a semiconductor device comprising forming a gate over a substrate, forming a source region and a drain region by doping a first portion and a second portion of active regions adjacent the gate, and forming a first recess in a portion of the source region and a second recess in a portion of the drain region. The method also includes activating the dopants in the source region and the drain region by heating the active regions and depositing a semiconductor material in the first recess and the second recess after activating the dopants in the source region and the drain region.Type: GrantFiled: March 1, 2005Date of Patent: March 25, 2008Assignee: Texas Instruments IncorporatedInventors: Periannan Chidambaram, Srinivasan Charkravarthi
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Patent number: 7344947Abstract: Methods fabricate DEMOS devices having varied channel lengths and substantially similar threshold voltages. A threshold voltage is selected for first and second devices. First and second well regions are formed. First and second drain extension regions are formed within the well regions. First and second back gate regions are formed within the well regions according to the selected threshold voltage. First and second gate structures are formed over the first and second well regions having varied channel lengths. A first source region is formed in the first back gate region and a first drain region is formed in the first drain extension region. A second source region is formed in the second back gate region and a second drain region is formed in the drain extension region.Type: GrantFiled: April 27, 2006Date of Patent: March 18, 2008Assignee: Texas Instruments IncorporatedInventors: Victor Ivanov, Jozef Czeslaw Mitros
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Patent number: 7345343Abstract: The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1053) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).Type: GrantFiled: August 2, 2005Date of Patent: March 18, 2008Assignee: Texas Instruments IncorporatedInventors: Tony T. Phan, William C. Loftin, John Lin, Philip L. Hower
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Patent number: 7345573Abstract: An integrated circuit structure including multiple thin film resistors having different sheet resistances and TCRs includes a first oxide layer (2) formed on a semiconductor substrate (1), a first thin film resistor (3) disposed on the first oxide layer (2), and a second oxide layer (14) disposed over the first oxide layer (2) and first thin film resistor (3). A second thin film resistor (15) is formed on the second oxide layer (14) and a third oxide layer (16) is formed over the second thin film resistor (15) and the second oxide layer (14). Interconnect metallization elements (12A,B & 22A,B) disposed on at least one of the second (14) and third (16) oxide layers electrically contact the circuit element (4), terminals of the first thin film resistor (3), and terminals of the second thin film resistor (15), respectively, through corresponding contact openings through at least one of the second (14) and third (16) oxide layers.Type: GrantFiled: May 24, 2005Date of Patent: March 18, 2008Assignee: Texas Instruments IncorporatedInventor: Eric W. Beach
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Patent number: 7346898Abstract: Multiple coprocessor scheduling of parallel processing steps control with bit arithmetic using a bitmask for each data block buffer indicating next processing step and a bitmask of processing steps with available coprocessors. ANDs of the bitmasks for the buffers with the bitmask of processing steps determines processing steps to run. This allows for parallel processing on the data blocks in the various buffers.Type: GrantFiled: January 29, 2003Date of Patent: March 18, 2008Assignee: Texas Instruments IncorporatedInventor: Christopher Tserng
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Patent number: 7344939Abstract: Ferroelectric memory cells (3) are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge loss at the cell storage node (SN) when the cell (3) is not being accessed while avoiding significant disruption of memory cell access operations. Methods (100, 200) are provided for fabricating ferroelectric memory cells (3) and ferroelectric capacitors (C), in which a parallel resistance (R) is integrated in the capacitor ferroelectric material (20) or in an encapsulation layer (46) formed over the patterned capacitor structure (C).Type: GrantFiled: December 7, 2006Date of Patent: March 18, 2008Assignee: Texas Instruments IncorporatedInventors: Jarrod Randall Eliason, Glen R. Fox, Richard A. Bailey
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Patent number: 7345600Abstract: Asynchronous sampling rate converter with input/output frequency ratio estimation and polyphase filtering uses FIFO level feedback to adaptively control frequency ratio estimation.Type: GrantFiled: March 9, 2006Date of Patent: March 18, 2008Assignee: Texas Instruments IncorporatedInventor: Stephen J. Fedigan
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Patent number: 7346026Abstract: A system and method for wireless local area network throughput enhancement includes an access point and an endpoint station in a wireless computer network transmitting data packets over radio frequency signals, and reordering the data packets into a megapacket in the access point using concatenation of the data packets. The method provides a significant throughput enhancement on wireless networks including IEEE 802.11 networks.Type: GrantFiled: January 21, 2004Date of Patent: March 18, 2008Assignee: Texas Instruments IncorporatedInventors: Itay Sherman, Lior Ophir, Igor Royzis, Fredy Rabih