Abstract: A semiconductor device is fabricated having a metal stress inducing layer that facilitates channel mobility. A gate dielectric layer is formed over a semiconductor substrate. The metal stress inducing layer is formed over the gate dielectric layer. The metal stress inducing layer has a selected conductivity type and is formed and composed to yield a select stress amount and type. A gate layer, such as a polysilicon layer, is formed over the metal stress inducing layer. The gate layer and the metal stress inducing layer are patterned to define gate structures.

Abstract: A semiconductor device comprising a gate structure on a semiconductor substrate and a recessed-region in the semiconductor substrate. The recessed-region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.

Abstract: The present invention provides, in one embodiment, a process for forming a dual work function metal gate semiconductor device (100). The process includes providing a semiconductor substrate (105) having a gate dielectric layer (110) thereon and a metal layer (205) on the gate dielectric layer. A work function of the metal layer is matched to a conduction band or a valence band of the semiconductor substrate. The process also includes forming a conductive barrier layer (210) on a portion (215) of the metal layer and a material layer (305) on the metal layer. The metal layer and the material layer are annealed to form a metal alloy layer (405) to thereby match a work function of the metal alloy layer to another of the conduction band or the valence band of the substrate. Other embodiments of the invention include a dual work function metal gate semiconductor device (900) and an integrated circuit (1000).

Abstract: The invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among others, may include forming one or more layers of material within an opening in a substrate, the opening and the one or more layers forming at least a portion of an isolation structure, and subjecting at least one of the one or more layers to an energy beam treatment, the energy beam treatment configured to change a stress of the one or more layers subjected thereto, and thus change a stress in the substrate.

Abstract: An electronic system (10). The system comprises circuitry (P1) for receiving a system voltage from a voltage supply. The system also comprises circuitry (141), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP1) and the critical path comprises a plurality of transistors. At least some transistors in the plurality of transistors have a corresponding predetermined voltage operating limit corresponding to a predicted lifespan. The system also comprises circuitry (221) for indicating a potential capability of operational speed of the critical path. The system also comprises circuitry (CB) for coupling the system voltage to the critical path. Lastly, the system also comprises circuitry (26) for adjusting the system voltage, as provided by the voltage supply, in response to the circuitry for indicating a potential capability.

Abstract: The present invention provides a method for removing photoresist, and a method for manufacturing a semiconductor device. The method for removing photoresist, without limitation, may include subjecting a photoresist layer (210) located over a substrate (110) to a thermal bake (410) in the presence of hydrogen, and then removing the photoresist layer (210).

Abstract: The present invention facilitates multi-zone furnace (102) based deposition processes by iteratively adjusting deposition time and zonal setpoint temperatures to mitigate deviations from desired target thickness(es). Coupled feedback loops are employed to update the deposition time (520) and the zonal setpoint temperatures (510) lot to lot and batch to batch while mitigating deviations fro the desired target thickness(es). Error checking is performed by computing an error metric (506) and only updating the setpoint temperatures on the error metric being within an acceptable value (508). Additionally, an excitation parameter (512) is determined that indicates variations in furnace operation.

Abstract: Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.

Abstract: The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer (133) and a first gate electrode layer (138) located over a substrate (110), wherein the first gate dielectric layer (133) has an amount of nitrogen located therein. In addition to the PMOS device (120), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device (160) having a second gate dielectric layer (173) and a second gate electrode layer (178) located over the substrate (110), wherein the second gate dielectric layer (173) has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device (120) and the NMOS device (160).

Abstract: A semiconductor device is fabricated with a protective liner and/or layer. Well regions and isolation regions are formed within a semiconductor body. A gate dielectric layer is formed over the semiconductor body. A gate electrode layer, such as polysilicon, is formed on the gate dielectric layer. A protective gate liner is formed on the gate electrode layer. A resist mask is formed that defines gate structures. The gate electrode layer is patterned to form the gate structures. Offset spacers are formed on lateral edges of the gate structures and extension regions are then formed in the well regions. Sidewall spacers are then formed on the lateral edges of the gate structures. An NMOS protective region layer is formed that covers the NMOS region of the device. A recess etch is performed within the PMOS region followed by formation of strain inducing recess structures.

Abstract: Disclosed herein is a device package that comprises a device having a top substrate that is disposed on a supporting surface of a package substrate. A package frame contacts the top surface of the top substrate and top surface of the package substrate, and hermetically seals the device between the top surfaces of the top substrate and package substrate. The device can be a semiconductor device, a microstructure such as a microelectromechanical device, or other devices.

Abstract: The invention relates to a single-poly EPROM comprising a source, a drain, a control gate, a floating gate and an additional gate. The control gate is positioned laterally of a channel between the source and the drain. The floating gate is positioned above the channel above the control gate. The additional gate is positioned above the floating gate, wherein the additional gate is electrically connected to the control gate.

Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).

Abstract: Gain errors are corrected in an ADC chip including an integrator (17), a comparator (30), and a digital filter (37) by storing a gain-adjusted LSB size based on measured gain error in a memory (44). The gain-adjusted LSB size is applied to the digital filter to cause gain-adjusted LSB size values to be added to or subtracted from accumulated content of the digital filter in accordance with a first or second state, respectively, of the comparator (30) during each cycle of the ADC. The final accumulated content after all required cycles of the ADC is a gain-corrected digital output signal (Dout(gain-corrected)).

Abstract: Multi-gate MOS transistors and fabrication methods are described, in which the transistor semiconductor body thickness or width is lithography independent, allowing scaled triple and quad-gate devices having semiconductor bodies smaller than a lateral gate length dimension. A form structure is provided over a semiconductor wafer starting structure, and spacers are formed along one or more sidewalls of an opening in the form structure. A semiconductor material is deposited in the opening by epitaxial growth or other deposition process, and the form structure and the spacer are removed. A gate structure is then formed along the top and sides of a central portion of the formed semiconductor body. The spacer may be L-shaped, providing an undercut or recess at the bottom of the semiconductor body sidewall, and the gate may be formed in the undercut area to allow fabrication of more than three gates.

Abstract: A broken trim die tool detection sensor. The lands of the tie bar die connect with the leads of the unit to form switches. The states of these switches indicate broken die lands or other malfunctions.

Abstract: A low-power data conversion system for converting a serial digital data input signal (DIN) to an analog output signal (Vout) by generating the serial digital data input signal (DIN) at a first sample rate (fsin) in a burst mode, wherein the sampling frequency of the serial digital data input signal (DIN) has a predetermined ratio to the frequency of an external reference clock signal (SLEEPCLK or WCLK). The serial digital data input signal (DIN) is converted into parallel format. A FIFO system temporarily stores a predetermined number of samples (Din) of the parallel format digital data input signal. The samples (Din) have a first sample rate (fsin). The samples (Din) are converted to an analog output signal (Vout).

Abstract: According to one embodiment of the present invention a method of reflecting light is disclosed including providing an element having a surface having an edge on which the element is capable of rolling and selectively reflecting light by rolling the surface such that a reflective element associated with the surface selectively reflects light to a desired location.

Abstract: An improved method for fabricating a window frame/window piece assembly is disclosed in this application. A window frame having an opening in its inner portion is provided. According to one aspect, the window frame can be formed from a unitary piece of sheet metal. A transparent piece is attached to the inner portion of the window frame through a molding process. According to one embodiment, the window frame is placed within a mold such that the inner portion of the window frame projects into an inner cavity inside the mold. After the mold has been closed, a transparent material is injected into the inner cavity so that it bonds with the inner portion of the window frame. After the bond of between the transparent material and the window frame is set, the window frame/window piece assembly is removed from the mold. According to another embodiment, a plurality of window frames may be loaded into a single mold so that a plurality of window frame/window piece assemblies can be fabricated in a single batch.

Abstract: An improved color processing method for use in imaging systems transforms the input color image components into an output set of color image components, at least one of which is transformed using a non-linear transformation function.