Abstract: A low noise current steering digital-to-analog converter (DAC). The DAC includes a current reference for generating a bias current that biases a set of current elements. The set of current elements includes a reference element. The current reference includes a reference amplifier and a reference arm. The reference arm includes a reference resistor and the reference element. The DAC further includes a switch periodically coupling each current element including the reference element, to the reference resistor and an output of the DAC. This rotates the set of current elements and attenuates flicker noise from each of the set of current elements.

Abstract: An apparatus and method for power management of a display system. A display controller couples to a memory storage device. A frame buffer in the memory storage device is filled with frames of information for display on a display device. The frames of information transfer to a display buffer in the display controller. The display controller transmits the frames of information from the display buffer to the display device. When frame information is not being transferred to the display controller, the display controller and the memory storage device may separately enter a power saving state. In power saving state, the display controller may continue to transmit frame information to the display device; however, power and a clock signal to components of display controller may be limited. When the display buffer is almost empty, the display controller exits power saving state to fill the display buffer.

Abstract: A method for streamlining error correction code computation while reading or programming a NAND flash memory. At least some of the illustrative embodiments are methods comprising transferring a data block between a flash memory and a memory controller, and computing an ECC for said data block while transferring the data block.

Abstract: Synchronization of downlink streaming data is performed by estimating the likelihood of an underflow or an overflow in an output buffer upon receipt of each encoded data frame to determine if synchronization will be needed. After each encoded data frame is decoded it is then synchronized if the estimate indicated synchronization would be needed. Synchronization of uplink steaming data is performed by estimating the likelihood of an underflow or an overflow in an input buffer upon sending of each encoded data frame to an output modem for transmission to determine if synchronization will be needed. If needed, synchronization will be performed later on a portion of data samples taken from the input buffer that are used to form a frame of un-encoded data samples.

Abstract: Methods and apparatus to provide an auxiliary receive path to support transmitter functions are disclosed. An example transceiver includes an antenna and a duplexer coupled to the antenna. A transmitter is coupled to the duplexer to output a transmit signal at a transmit frequency. A receiver is coupled to the duplexer to receive a received signal at a receiver frequency. A signal processor is coupled to the transmitter and receiver. An auxiliary receiver is communicatively coupled to the signal processor to receive the transmit signal output from the transmitter and send an auxiliary receiver signal to the signal processor. The signal processor adjusts the transmit signal based on the auxiliary receiver signal.

Abstract: A novel mechanism that is operative to observe and compare the differentiated phase of the reference and variable PLL loop signals using a frequency detector. The resultant phase differentiated error is then accumulated to yield the phase error. The operation of the loop with the frequency detector is mathematically equivalent to that of the phase detector. A frequency error accumulator is used to generate the integral of the frequency error. The frequency error accumulator also enables stopping the accumulation of the frequency upon detection of a sufficiently large perturbation, effectively freezing the operation of the loop as subsequent frequency error updates are not accumulated. Upon removal of the phase freeze event, accumulation of the frequency error and consequently normal loop operation resumes.

Abstract: Measuring surface profiles of structures on integrated circuits is difficult when feature sizes are less than 100 nanometers. Atomic force microscopy provides surface profile measurement capability on flat horizontal surfaces, but has difficulty with three-dimensional structures such as MOS transistor gates, contact and via holes, interconnect trenches and photoresist patterns. An atomic force microscopy probe with two atomically sharp tips configured to facilitate measurements of three-dimensional structures is disclosed. A method of making such measurements using the disclosed probe and a method of fabricating an IC encompassing the method are also claimed.

Abstract: System and method for providing additional channels to an existing communications system. A preferred embodiment comprises a coprocessor (such as coprocessor 215) coupled to a modem (such as modem 205), wherein transmissions from the modem are routed to the coprocessor. The coprocessor then can insert transmissions that use the additional channels into the transmission from the modem. Timing consistency can be ensured by the coprocessor using scrambling and channelization codes that are provided by the modem. The use of the coprocessor can allow the use of an existing design for the modem rather than creating a new design when a revision to a technical standard is released, saving time and money for equipment manufacturers.

Abstract: Embodiments of a system for processing a signal may include a receiver configured to receive an input analog signal and an up converter coupled with the receiver and configured to up convert the analog signal to an up converted analog signal. Embodiments may further include an amplifier coupled with the up converter and configured to amplify the up converted analog signal to generate an amplified signal and also a bandpass filter coupled with the amplifier and configured to filter the amplified signal to generate a filtered analog signal. According to embodiments, the filtered analog signal may be fed to a quanitizer of the ADC. Intermediate signals made thus avoid the flicker noise region typically associated with an integrator of the ADC and may minimize the quantization noise associated with converting higher frequency analog signals.

Abstract: A novel and useful mechanism for automatically establishing a radio link between a communications device and a commercially available FM radio receiver, thereby eliminating the need to manually configure both the target FM radio receiver and the FM transmitter to a suitable FM station. The mechanism scans the RF spectrum periodically for candidate frequencies over which to transmit the desired audio signal to the target radio. Once a suitable frequency is detected, the mechanism waits for an incoming call in the case of a cellular phone or immediately establishes a link such as in the case of a multimedia player. When a connection is to be established, a Radio Data System compatible bitstream is transmitted to configure the target radio to jump to an “alternate frequency” when reception conditions are poor enough. To ensure that the target radio receiver jumps to the desired station, the FM transmitter sends a CW signal to jam or block the station the target radio is currently tuned to.

Abstract: One embodiment of the present invention includes an adaptive voltage scaling system associated with an integrated circuit (IC). The system comprises at least one target performance circuit comprising a first semiconductor material and being configured to determine at least one voltage potential in response to achieving a target performance based on an applied voltage. The system also comprises a controller configured to set an output of a variable power supply to the determined at least one voltage potential, and an aging controller configured to control the at least one target performance circuit to age the first semiconductor material at a rate that is at least substantially commensurate with a rate at which other circuitry in the IC ages.

Abstract: An electronic circuit includes a storage circuit and a microprocessor operable together with the storage circuit as a speech coder. The speech coder has a backward pitch enhancement in frames or subframes having a length and at least one main pulse and at least one backward pitch enhancement pulse preceding the main pulse by a portion of the length called a pitch lag, and is operable to limit in number any such backward pitch enhancement pulse or pulses to a predetermined maximum number more than none upon an occurrence when the length divided by the pitch lag is at least one more than that maximum number. Other forms of the invention involve systems, circuits, devices, processes and methods of operation.

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.

Abstract: The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, without limitation, may include providing a substrate having a sub-surface feature and a surface feature, and determining a location of the sub-surface feature relative to the surface feature using a scatterometer.

Abstract: Deblur digital camera image captured in low-light, long-integration-time conditions by deconvolution based on motion estimation from preceding and following reference images. Alternatively, capture multiple short-integration-time images and fuse after motion estimation and alignment.

Abstract: In accordance with an embodiment of the invention, there is a method of designing a lithography mask. The method can comprise determining a maximum width of a shifter, wherein the maximum width corresponds to a width of a shifter for a first set of features and determining whether the shifter having the maximum width can be placed in a shifter space for a second set of features. The method can also comprise incrementally decreasing the width of the shifter to be placed into the shifter space for the second set of features when the shifter having the maximum width cannot be placed in the shifter space for a feature in the second set of features until an acceptable shifter width can be determined or until the shifter width is reduced to a predetermined minimum shifter width.

Abstract: A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.

Abstract: A processor (1700) for processing instructions has a pipeline (1710, 1736, 1740) including a fetch stage (1710) and an execute stage (1870), a first storing circuit (aGHR 2130) associated with said fetch stage (1710) and operable to store a history of actual branches, and a second storing circuit (wGHR 2140) associated with said fetch stage (1710) and operable to store a pattern of predicted branches, said second storing circuit (wGHR 2140) coupled to said first storing circuit (aGHR 2130), said execute stage (1870) coupled back to said first storing circuit (aGHR 2130). Other processors, wireless communications devices, systems, circuits, devices, branch prediction processes and methods of operation, processes of manufacture, and articles of manufacture, as disclosed and claimed.

Abstract: A detector and detection method for identifying unknown chemical solutions following chemical spills includes a specific gravity detector including a detector column having an inlet end operable to collect a sample of a solution, wherein the detector column is formed of an optically transparent material to allow visual observation of the sample in the detector column. At least a first plurality of specific gravity floats including a first specific gravity float is located and moveable within the detector column, wherein the first specific gravity float has a density to float in liquids having a specific gravity of greater than a first density level. At least a second specific gravity float is located and moveable within the detector column, wherein the second specific gravity float has a density to float in liquids having a specific gravity greater than the first density level. A sample of an unknown solution from a site of a chemical spill is introduced into the detector column.

Abstract: A method for changing an effective capacitance of an amplifier circuit having a match transistor and a coupled cascode transistor includes changing an on-state of at least one of a plurality of sub-transistors of the match transistor. The method further includes changing a transconductance of the match transistor as a function of the change of the on-state. The method further includes changing an equivalent resistance, as measured between a source and a drain of the cascode transistor, as a function of the change of the transconductance of the match transistor.