Abstract: A method and apparatus for electroplating metallized bumps of substantially uniform height on predetermined terminal areas of a substrate. Cup plating apparatus includes elements for adjusting parameters affecting the geometry of the substrate relative to the plating cup, as well as flow rate of the electroplating solution against the substrate surface. By achieving non-laminar flow of the electroplating solution near the substrate edges, the plating characteristics of the electroplating solution are altered in this region, substantialy offsetting "edge effect", so that the resulting plated bump height is substantially uniform across the substrate.

Abstract: A multi-processor, multi-bus system comprises a host processor and a cluster controller coupled to a first type of bus; a local processor coupled to a second type of bus; and bus interface circuits coupled to the first and second bus types for selectively enabling the second bus to be coupled to the host processor, and for selectively enabling the first bus to be coupled to the local processor. Both bus types are asynchronous. Each bus interface circuit comprises a first-in-first-out (FIFO) register, interrupt logic, and transmitter/receiver logic. The pair of bus interface circuits together provide dual simplex data transfer between the local processor and the cluster controller which is directed by a parallel data ling (PDL) protocol. The protocol utilizes a 16-bit wide control word. The most significant bit 15, referred to as the command bit, is a "one" whenever bits 0-7 contain a command byte, while the command bit is "zero" whenever bits 0-7 contain a data byte.

Abstract: A localized circuit card cooling device is mounted adjacent to a target circuit card in an unused circuit card mounting location of an electronic system enclosure to provide localized cooling to the target circuit card or a predetermined portion thereof.

Abstract: A multi-processor, multi-tasking virtual machine comprises processes, messages, and contexts. Processes communicate only through messages. Contexts are groups of related processes. The virtual machine is implemented in a distributed data processing system comprising a plurality of individual cells coupled by a local area network (LAN). Each cell may comprise one or more processes and/or contexts.A network interface module (NIM) provides the interface between any individual cell and the LAN. To facilitate message transmission between processes resident on different cells, each NIM is provided with tables identifying the locations of resident and non-resident processes, respectively. Cells may be added to or deleted from the LAN without disrupting the LAN operations.

Abstract: A hospital information system comprises a data processing system including a plurality of terminals having display means and data entry means. Patient information is entered into the system via the terminals, is organized hierarchically in the system, and may be displayed to users having proper access to the system. Once a patient is selected from a census list, all further access to information concerning such patient is obtained in a two-level selection process by (1) selecting a descriptor corresponding to information at a first organizational level, and (2) selecting a descriptor corresponding to information at a second organization level. Various parameters can be added to or deleted from the information at the second organizational level on a patient-specific basis by an authorized system user. Certain parameters may be "pre-printed", and other parameters may represent "macro"parameters.

Abstract: A multi-processor, multi-tasking virtual machine comprises processes, messages, and contexts. Processes communicate only through messages. Contexts are groups of related processes.The virtual machine makes all hardware devices appear to be processes, in that the occurrence of an event on a device causes a message to be generated and sent to another process for handling. The receiving process performs all operations required to handle the event. Thus a variety of hardware devices can be connected and disconnected from the system without interrupting its operation and without necessitating extensive software revisions.

Abstract: A memory management unit (MMU 12, FIG. 1) is provided which allocates space in a memory unit (2, FIG. 1) to a number of user tasks being performed concurrently by a CPU (5, FIG. 1). The MMU is capable of dynamically changing the number of concurrent user tasks and the page allocation for each task. The MMU also allows direct memory accesses into the address space of any user task.

Abstract: A multi-processor, multi-tasking virtual machine comprises processes, messages, and contexts. Processes communicate only through messages. Contexts are groups of related processes. The virtual machine is implemented in a distributed data processing system comprising a plurality of individual cells coupled by a local area network (LAN). Each cell may comprise one or more processes and/or contexts.A network interface module (NIM) provides the interface between any individual cell and the LAN. To facilitate message transmission between processes resident on different cells, each NIM is provided with tables identifying the locations of resident and non-resident processes, respectively. Cells may be added to or deleted from the LAN without disrupting the LAN operations.

Abstract: A disk drive shock mount is provided which attenuates shocks and vibrations to a disk drive (1, FIG. 1). The mount comprises a cradle 20 which is affixed to the disk drive housing, and a mounting plate 10 which may be used to suitably secure the disk drive assembly 1 to the next higher level of assembly. Flexible, compressible vibration isolators 50 of rubber or plastic are used to couple the cradle to the mounting plate. Rigid pins 70 on the cradle mate with grommet-enclosed apertures 60, 61 in the mounting plate to limit the degrees of motion permitted between the cradle and the mounting plate.

Abstract: A pipelined digital computer processor system (10, FIG. 1) is provided comprising an instruction prefetch unit (IPU,2) for prefetching instructions and an arithmetic logic processing unit (ALPU, 4) for executing instructions. The IPU (2) has associated with it a high speed instruction cache (6), and the ALPU (4) has associated with it a high speed operand cache (8). Each cache comprises a data store (84, 94, FIG. 3) for storing frequently accessed data, and a tag store (82, 92, FIG. 3) for indicating which main memory locations are contained in the respective cache.The IPU and ALPU processing units (2, 4) may access their associated caches independently under most conditions. When the ALPU performs a write operation to main memory, it also updates the corresponding data in the operand cache and, if contained therein, in the instruction cache permitting the use of self-modifying code. The IPU does not write to either cache.

Abstract: An electronic workstation comprising a detachable keyboard (10, FIG. 1) associated with the workstation for permitting operator interface to same. The workstation comprises a base (2) with an upper surface (15) inclined towards the operator, a viewable element (8) such as a CRT screen, and a support (4,6) for supporting the viewable element relative to the base. The keyboard 10 is positionable by the operator in any of several orientations relative to the base 2. In one orientation the keyboard is fully incumbent upon the base, thereby maintaining the workstation profile or "footprint" relative to a work surface (30) at a minimum. In another orientation the keyboard rests only partially on the work surface. Protuberances (24, 34) on the upper surface of the base register with corresponding indentations in the lower surface of the keyboard to facilitate locking the keyboard in the desired position relative to the base.

Abstract: A multi-processor, multi-tasking virtual machine comprises processes, messages, and contexts. Processes communicate only through messages. Contexts are groups of related processes. The virtual machine is implemented in a distributed data processing system comprising a plurality of individual cells coupled by a local area network (LAN). Each cell may comprise one or more processes and/or contexts.A network interface module (NIM) provides the interface between any individual cell and the LAN. To facilitate message transmission between processes resident on different cells, each NIM provides addressing modes allowing messages to be sent to processes according to the processes' names. Cells may be added to or deleted from the LAN, and processes may be created or deleted, without disrupting the LAN operations.

Abstract: A direct memory access controller (8, FIG. 1) is provided which can service a number of input/output controllers (24, 26) concurrently on a time-division multiplexed basis. The direct memory access controller 8 (DMAC) is capable of interconnecting more than one input/output device (64, 66, 69, 74, 76) with more than one system memory (2, 20). The DMAC 8 can also transfer data from one system memory (2) to a second system memory (20), or within one system memory.

Abstract: In a system including a central processor, central memory, and local video controller communicating with a video terminal, the video terminal including a terminal processor and a video memory for storing video information for displaying on the terminal screen, a change detect circuit is provided in the local video controller for detecting whenever a change has occurred in that portion of the central memory containing video information to be displayed on the terminal's video screen. Responsive to the change detect circuit, the local video controller sends updated video information to the video memory at the terminal.The change detect circuit reduces the workload on the system by sending only the updated video information to the terminal.The change detect circuit is capable of operation with a system employing multiple terminals each having multiple independent screen display areas.

Abstract: A Complementary Metal Oxide Semiconductor (CMOS) input buffer circuit is provided which accepts Transistor-Transistor Lock (TTL) input signal levels without generating any significant DC current path. A reference voltage circuit (1, FIG. 1) provides first and second reference voltages (V.sub.A and V.sub.B, FIG. 1) which are coupled to first and second stages, respectively, of the input buffer circuit (3, FIG. 1), and which are of predetermined magnitudes and scaled relative to each other to permit the P-channel devices of the input buffer circuit to turn off completely when the input to the circuit is "high", while allowing a successively higher output at each successive stage of the input buffer circuit. The reference circuit 1 is compensated for power supply and process window variations.

Abstract: In a video terminal comprising a terminal processor communicating with a central processor, and a single-block non-interleaved video memory for storing video information for displaying on the terminal screen, a video update FIFO buffer is provided for buffering video information between the terminal processor and the video memory. The 3-word FIFO buffer is filled during screen trace, and it transfers its contents into the video memory during screen retrace periods.The FIFO buffer permits screen information to appear without flicker. It also permits scrolling of row segment screen information by reading a row segment from the video memory, temporarily storing it, and then writing it into an adjacent row segment. It also permits flexible cursor symbols, cursor blinking of individual display screen areas, and certain data format conversions.

Abstract: In an intelligent video terminal communicating with a central processor, a video memory controller is provided which performs a variety of data transfer operations in response to commands from a terminal processor. The data transfer operations include block reads and block writes, copying an entire screen data line or a portion thereof, scrolling an entire screen line or a portion thereof, filling a screen line or a portion thereof with a desired character, and independently scrolling a row segment within each of multiple independent screen display areas. In addition, the current location of the cursor within each screen display area can be monitored.Many of the data transfer operations are performed by the video memory controller in response to a single terminal processor command, thereby minimizing terminal processor interrupts.

Abstract: A printed wiring assembly card insertion/extraction tool is provided of circular cross-section with a cam-like member at one end. Each card within the card cage has a tab centrally located along one edge, the tab containing a keyhole-like aperture. When the cards are in their normal side-by-side position within the card cage, all of the apertures line up with a similarly shaped aperture in a support bracket mounted on one side of the card cage, such that the insertion/extraction tool may be inserted through the apertures. A selected card may be extracted by appropriate rotation of the tool about its axis, whereby the cam-like member engages the corresponding aperture of the selected card and forces it out. Likewise, cards may be inserted by reversal of the process. A retaining bracket is provided on the opposite side of the card cage opening from the support bracket.

Abstract: A logic array which is small in size and low in power dissipation uses only one clock signal. The array is fully precharged by precharging a first portion and a second portion and then applying ground to the first portion while delayably applying the ground to the second portion. The address is read into the first portion during the precharging to speed up operation of the array.