Patents Represented by Attorney, Agent or Law Firm Warren L. Franz
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Patent number: 8120281Abstract: According to one embodiment of the disclosure, a light beam control system includes a positive intrinsic negative diode coupled to a controller circuit. The positive intrinsic negative diode receives a portion of a light beam generated by a light source and converts the portion into a measured intensity. The controller circuit receives the measured intensity, determines an output signal according to the measured intensity and a reference, and adjusts the light beam according to the output signal.Type: GrantFiled: November 29, 2007Date of Patent: February 21, 2012Assignee: Texas Instruments IncorporatedInventor: Fred J. Reuter
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Patent number: 8120155Abstract: A MEMS device is packaged in a process which hydrogen (H) deuterium (D) for reduced stiction. H is exchanged with D by exposing the MEMS device with a deuterium source, such as deuterium gas or heavy water vapor, optionally with the assistance of a direct or downstream plasma.Type: GrantFiled: July 31, 2008Date of Patent: February 21, 2012Assignee: Texas Instruments IncorporatedInventors: Earl V. Atnip, Simon Joshua Jacobs
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Patent number: 8119470Abstract: Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.Type: GrantFiled: March 21, 2007Date of Patent: February 21, 2012Assignee: Texas Instruments IncorporatedInventors: Shashank Sureshchandra Ekbote, Borna Obradovic, Lindsey Hall, Craig Huffman, Ajith Varghese
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Patent number: 8121482Abstract: A reconfigurable optical add-drop multiplexer (ROADM) and a method of passing at least one optical channel through the multiplexer. In one embodiment, the multiplexer includes: (1) a main input port, (2) a main output port, (3) an add input port, (4) a drop output port, (5) dispersive optics configured spatially to spread and recombine optical spectra containing optical channels and (6) a spatial light modulator having an integral, lateral-gradient volume Bragg grating and configured to assume a bar state in which at least one of the optical channels is passed from the main input port to the main output port and at least another of the optical channels is passed from the add input port to the drop output port and a cross state in which the integral, lateral-gradient volume Bragg grating is transmissive with respect to the channels.Type: GrantFiled: September 15, 2008Date of Patent: February 21, 2012Assignee: Texas Instruments IncorporatedInventor: Sajjad A. Khan
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Patent number: 8114744Abstract: A method of fabricating an integrated circuit (IC) including a plurality of MOS transistors and ICs therefrom include providing a substrate having a silicon including surface, and forming a plurality of dielectric filled trench isolation regions in the substrate, wherein the silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. A first silicon including layer is deposited, wherein the first silicon including extends from a surface of the trench isolation regions over the trench isolation active area edges to the silicon including surface. The first silicon including layer is completely oxidized to convert the first silicon layer to a silicon oxide layer, wherein the silicon oxide layer provides at least a portion of a gate dielectric for at least one of the plurality of MOS transistors.Type: GrantFiled: December 29, 2008Date of Patent: February 14, 2012Assignee: Texas Instruments IncorporatedInventors: Amitava Chatterjee, Seetharaman Sridhar, Xiaoju Wu, Vladimir F. Drobny
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Patent number: 8113662Abstract: In accordance with the teachings of the present disclosure, a system and method for displaying an image are provided. In one embodiment, the method includes receiving a laser through a rotary diffuser. The rotational speed of the rotary diffuser may be continuously varied to reduce the effect of an image artifact in a light pattern. The image artifact may be caused by an imperfection in the rotary diffuser. The light pattern is projected on a display device.Type: GrantFiled: January 22, 2009Date of Patent: February 14, 2012Assignee: Texas Instruments IncorporatedInventor: Stephen W. Marshall
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Patent number: 8114729Abstract: A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and pre-gate etch implant of a first dopant type into an unmasked portion of the polysilicon layer is performed, wherein masked portions of the polysilicon layer are protected from the first dopant. The polysilicon layer is patterned to form a plurality of polysilicon gates and a plurality of polysilicon lines, wherein the masked portion includes at least one of the polysilicon lines which couple a polysilicon gate of a PMOS device to a polysilicon gate of an NMOS device.Type: GrantFiled: October 10, 2007Date of Patent: February 14, 2012Assignee: Texas Instruments IncorporatedInventors: Shashank Ekbote, Kamel Benaissa, Greg C. Baldwin, Borna Obradovic
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Patent number: 8115866Abstract: Given an incoming stream of interlaced video, data for each field is analyzed to detect a progressive frame cadence. If a progressive frame cadence is detected, a set of instructions is generated to instruct a de-interlacing unit which fields were mastered from the same progressive frame. The similarity in motion between two consecutive fields and the correlation between two consecutive fields is used to detect the presence of cadences and breaks in cadences. Breaks in cadences are continuously detected in order to characterize the source as video and prevent false detection of cadences.Type: GrantFiled: December 29, 2006Date of Patent: February 14, 2012Assignee: Texas Instruments IncorporatedInventor: Marshall Charles Capps
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Patent number: 8114728Abstract: A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of the NMOS transistor and the polysilicon gate electrode of the PMOS transistor, and then removing the gate electrode of the NMOS transistor. The method also includes depositing a NMOS-metal layer over the semiconductor substrate, depositing a fill-metal layer over the NMOS-metal layer, and then reducing the thickness of the NMOS metal layer and the fill metal layer to expose the gate electrodes of the NMOS transistor and the PMOS transistor.Type: GrantFiled: March 25, 2010Date of Patent: February 14, 2012Assignee: Texas Instruments IncorporatedInventor: Michael Francis Pas
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Patent number: 8114731Abstract: The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a semiconductor substrate (105), and an insulator (130) located over the first capacitor plate (120), at least a portion of the insulator (130) comprising an interlevel dielectric layer (135, 138, 143, or 148). The integrated high voltage capacitor further includes capacitance uniformity structures (910) located at least partially within the insulator (130) and a second capacitor plate (160) located over the insulator (130).Type: GrantFiled: November 24, 2008Date of Patent: February 14, 2012Assignee: Texas Instruments IncorporatedInventors: David L. Larkin, Lily X. Springer, Makoto Takemura, Ashish V. Gokhale, Dhaval A. Saraiya
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Patent number: 8116005Abstract: For combining light from different light sources in a light source, dichroic filters are displaced individually according to the physical arrangement of the light sources such that the reflected light from the dichroic filters is coincident in angle and space.Type: GrantFiled: April 4, 2008Date of Patent: February 14, 2012Assignee: Texas Instruments IncorporatedInventors: Andrew Gerritt Huibers, Regis Grasser
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Patent number: 8109485Abstract: A display wall mount comprising a wall bracket configured to couple to a wall and having a first wall bracket edge, a display bracket configured to couple to the display and having a first display bracket edge, and a curvilinear bar moveably coupled between the first wall bracket edge and the first display bracket edge. The display bracket is moveably coupled to the wall bracket.Type: GrantFiled: May 14, 2007Date of Patent: February 7, 2012Assignee: Texas Instruments IncorporatedInventors: Lee T. VanLanen, Douglas M. Galletti
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Patent number: 8110416Abstract: Defects in components in ICs which may cause circuit failures during operation of the IC are often difficult to detect during and immediately after fabrication of the IC by DC test methods. A method of testing components to detect such defects using AC Impedance Spectroscopy is disclosed. Data may be analyzed using Nyquist plots and Bode plots. Nyquist plots of typical defect types are disclosed. Components may include MOS transistor gate structures, contacts, vias and metal interconnect lines. Components tested may be contained in integrated circuits or in test circuits. Integrated circuits containing components tested by AC Impedance Spectroscopy may be partially fabricated or deprocessed after fabrication.Type: GrantFiled: December 4, 2008Date of Patent: February 7, 2012Assignee: Texas Instruments IncorporatedInventors: Alfred J Griffin, He Lin
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Patent number: 8110462Abstract: The present invention relates to electrostatic discharge (ESD) protection circuitry. Multiple techniques are presented to adjust one or more ends of one or more fingers of an ESD protection device so that the ends of the fingers have a reduced initial trigger or breakdown voltage as compared to other portions of the fingers, and in particular to central portions of the fingers. In this manner, most, if not all, of the adjusted ends of the fingers are likely to trigger or fire before any of the respective fingers completely enters a snapback region and begins to conduct ESD current. Consequently, the ESD current is more likely to be distributed among all or substantially all of the plurality of fingers rather than be concentrated within one or merely a few fingers. As a result, potential harm to the ESD protection device (e.g., from current crowding) is mitigated and the effectiveness of the device is improved.Type: GrantFiled: February 16, 2006Date of Patent: February 7, 2012Assignee: Texas Instruments IncorporatedInventor: Robert Michael Steinhoff
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Patent number: 8110454Abstract: A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconductor region that differs from the first semiconductor region. An interface exists between the first semiconductor region and the second semiconductor region. The transistor also comprises a voltage tap region comprising at least a portion located in a position that is closer to the interface than the drain region. A mixed technology circuit is also described.Type: GrantFiled: September 2, 2009Date of Patent: February 7, 2012Assignee: Texas Instruments IncorporatedInventor: Sameer P. Pendharkar
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Patent number: 8112737Abstract: A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are selected. The selected critical cells are altered with respect to contact resistance and/or contact capacitance. The map including the altered cells is provided as the design layout.Type: GrantFiled: September 19, 2008Date of Patent: February 7, 2012Assignee: Texas Instruments IncorporatedInventors: Nagaraj N. Savithri, Dharin Nayeshbhai Shah, Girishankar Gurumurthy
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Patent number: 8110857Abstract: A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.Type: GrantFiled: February 26, 2010Date of Patent: February 7, 2012Assignee: Texas Instruments IncorporatedInventors: Pinghai Hao, Imran Khan, Joe Trogolo
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Patent number: 8094352Abstract: A mirror device and a method for manufacturing the mirror device are presented. The mirror device includes a mirror formed from a first substrate and a hinge/support structure formed from a second substrate. The hinge/support structure includes a recessed region and a torsional hinge region. The mirror is coupled to the hinge/support structure at the recessed region. Further, a driver system is employed to cause the mirror to pivot about the torsional hinge region.Type: GrantFiled: May 13, 2008Date of Patent: January 10, 2012Assignee: Texas Instruments IncorporatedInventor: John W. Orcutt
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Patent number: 8093716Abstract: The present invention provides a semiconductor device fuse, comprising a metal layer and a first semiconductor layer that electrically couples the metal layer to a fuse layer, wherein the fuse layer is spaced apart from the metal layer. The semiconductor device fuse further comprises a second semiconductor layer that forms a blow junction interface with the fuse layer. The blow junction interface is configured to form an open circuit when a predefined power is transmitted through the second semiconductor layer to the fuse layer.Type: GrantFiled: July 29, 2005Date of Patent: January 10, 2012Assignee: Texas Instruments IncorporatedInventors: Robert L. Pitts, Bryan Sheffield, Roger Griesmer, Joe McPherson
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Patent number: 8093622Abstract: A semiconductor device having a thyristor SCR with reduced turn-off time. A third semiconductor region of the second conductivity type (anode AN) and a fourth semiconductor region of the first conductivity type (anode gate AG) are formed in the top layer of a first semiconductor region; fifth semiconductor region of the first conductivity type (cathode CA) and sixth semiconductor region of the second conductivity type (cathode gate CG) are formed in the top layer of a second semiconductor region; a gate insulating film and gate electrode MG are formed on the second semiconductor region. When the thyristor is turned off from the on state, a higher potential than that on the anode is applied to the anode gate, and a diode made up of the anode and the anode gate inside the thyristor is made to conduct so as to control the potential of the anode during driving.Type: GrantFiled: August 1, 2008Date of Patent: January 10, 2012Assignee: Texas Instruments IncorporatedInventors: Hideaki Kawahara, Toshimi Satoh, Toshiyuki Tani