Patents Represented by Attorney Warren M. Becker
  • Patent number: 4409592
    Abstract: In a data communications systems having a communications channel (3) for interconnecting a plurality of transceivers (1) and (2), each of said transceivers (1) and (2) including means (80) for transmitting a signal having transitions, there is provided a means (20) responsive to the presence and absence of a signal on said communications channel (3) during a transition of a signal transmitted by said transmitting means (80) for providing a collision detected (CD) signal if there is destructive interference with the transmitted signal on said communication channel (3) during a transition of said transmitted signal and means (48) responsive to said CD signal for terminating said transmitting of said signal.
    Type: Grant
    Filed: April 20, 1981
    Date of Patent: October 11, 1983
    Inventor: V. Bruce Hunt
  • Patent number: 4396979
    Abstract: A microprocessor for facilitating the execution of instructions which require repetitive shift and arithmetic logic unit operations comprises an arithmetic logic unit having a first and a second input and an output, a plurality of registers, at least one of which is a bidirectionally shifting register and multiplexing apparatus for selectively coupling each of said plurality of registers to said first and said second inputs and said output of said arithmetic logic unit.
    Type: Grant
    Filed: May 30, 1980
    Date of Patent: August 2, 1983
    Assignee: Fairchild Camera & Instrument Corporation
    Inventors: Yeshayahu Mor, Allan M. Schiffman
  • Patent number: 4393476
    Abstract: A discharge circuit for rapidly discharging the word lines of random access memories to thereby prevent erroneous reading from or writing into the memory during periods when the word lines are in a mid-state transition between selected and deselected voltage levels. Each discharge circuit associated with the memory word lines includes a transistor that is conductive only when a full select voltage level is applied to the word line and which controls conduction of a second multi-collector transistor coupled between top and bottom lines of a word line pair and a current source to discharge the word line pair during the mid-state transition period and to thus increase the speed capabilities of the memory.
    Type: Grant
    Filed: July 13, 1981
    Date of Patent: July 12, 1983
    Assignee: Fairchild Camera & Instrument Corp.
    Inventor: Warren R. Ong
  • Patent number: 4388855
    Abstract: A slide decelerator assembly for a firearm (1), having a slide (2) which moves rearwards when the firearm (1) is fired is described comprising means (12, 13) for compressing air in response to said rear movement of said slide 2for retarding said rear slide movement.
    Type: Grant
    Filed: October 6, 1980
    Date of Patent: June 21, 1983
    Inventor: Paul J. Sokolovsky
  • Patent number: 4384353
    Abstract: A semiconductor digital memory such as a charge coupled device is provided with error detection capability. Error logic responsive to a group of data on the input bus generates a first error code which is stored in memory along with the group of data. When the data is retrieved from memory similar error logic generates a second error code. The first and second error codes are compared, and if the codes are identical the data is assumed to be correct. If codes differ then the data is discarded or errors therein are identified and corrected.
    Type: Grant
    Filed: February 19, 1981
    Date of Patent: May 17, 1983
    Assignee: Fairchild Camera and Instrument Corp.
    Inventor: Ramesh C. Varshney
  • Patent number: 4377844
    Abstract: A memory addressing apparatus (1,20,90) is described comprising a circuit (5,26,96) responsive to a current external memory address on an input line (2,21,91) and a signal generated by an auxiliary memory circuit (8,29,93) for providing a current internal address for addressing an internal memory (15,19,101). For maximum program security, the above described components are all located in a single integrated circuit package.
    Type: Grant
    Filed: February 20, 1980
    Date of Patent: March 22, 1983
    Inventor: Marc Kaufman
  • Patent number: 4374011
    Abstract: A method for fabricating insulating regions in an integrated circuit structure is disclosed in which the insulating regions do not encroach upon the surrounding integrated circuit and in which a substantially planar surface across the top of the insulating material and the substrate is created. The method includes the steps of removing portions of the substrate wherever the insulating regions are to be formed, beginning to deposit insulating material across the substrate and in the openings created, and, while continuing to deposit insulating material simultaneously removing insulating material from generally horizontal surfaces and redepositing it on generally vertical surfaces of the substrate and the openings until a planar surface results.
    Type: Grant
    Filed: May 8, 1981
    Date of Patent: February 15, 1983
    Assignee: Fairchild Camera & Instrument Corp.
    Inventors: Madhukar B. Vora, Werner F. Rust
  • Patent number: 4370737
    Abstract: A sense amplifier for determining the binary logic state of a dynamic memory cell (11.sub.x,y) preamplifies an initial voltage difference established between a first input line (17.sub.y) coupled to the memory cell (11.sub.x,y) and a first reference line (18.sub.y) coupled to a reference cell (32.sub.y). The resulting amplifies voltage difference is generated between a second input line (19) coupled through a coupling device (Q51.sub.y) to the first input line (17.sub.y) and a second reference line (20) coupled through another coupling device (Q52.sub.y) to the first reference line (18.sub.y) by capacitively charging the second lines (19 and 20) preferably with a pair of capacitors (C61 and C62) individually coupled to the second lines (19 and 20). A differential sensing device (90) senses the amplified voltage difference to determine the logic state which is fully restored to the memory cell (11.sub.x,y).
    Type: Grant
    Filed: February 11, 1980
    Date of Patent: January 25, 1983
    Assignee: Fairchild Camera and Instrument Corporation
    Inventor: John Y. Chan
  • Patent number: 4368420
    Abstract: A temperature-compensated reference voltage circuit includes a transistor having a positive temperature coefficient of current. A circuit for establishing a predetermined current in the positive-temperature-coefficient-of-current transistor is connected to that transistor. A predetermined resistance serially connects the positive-temperature-coefficient-of-current transistor with a transistor having negative temperature coefficient of base-to-emitter voltage. The temperature-compensated reference voltage is established between the transistors. The temperature-compensated reference voltage circuit is particularly useful in a supply voltage sense amplifier circuit for thermal printhead drive transistors or other load elements. The sense amplifier circuit includes a circuit for comparing the reference voltage and a supply voltage. An output is adapted to be connected to a load for receiving the supply voltage.
    Type: Grant
    Filed: April 14, 1981
    Date of Patent: January 11, 1983
    Assignee: Fairchild Camera and Instrument Corp.
    Inventor: James R. Kuo
  • Patent number: 4355938
    Abstract: An automatic work piece changer for a milling machine and the like is described. In the work piece changer there is provided a work piece hopper (2) for storing a plurality of work pieces to be movable, a carriage assembly (3) for removing work pieces from the hopper (2) to a work station where they are machined, a clamping assembly (6) for holding each of the work pieces in the work station so as to prevent their movement during the machining thereof and an ejecting assembly (60) for ejecting machined work pieces from the changer after they are machined. Operation of the work piece changer is controlled by signals received from the milling machine in a conventional manner.
    Type: Grant
    Filed: June 4, 1979
    Date of Patent: October 26, 1982
    Inventor: Jeffrey L. Page
  • Patent number: 4354257
    Abstract: A sense amplifier for use with a charge coupled device in which capacitive coupled charge is employed with a flip-flop circuit to accelerate sense and readout. Operation of the amplifier is effected with two external clocks and two internally generated clocks.
    Type: Grant
    Filed: May 23, 1980
    Date of Patent: October 12, 1982
    Assignee: Fairchild Camera and Instrument Corporation
    Inventors: Ramesh C. Varshney, Kalyanasundaram Venkateswaran
  • Patent number: 4352492
    Abstract: A video game apparatus for connection to a standard television set and including an electronics-containing console having a plurality of parameter selection buttons and a chute mechanism for receiving a replaceable cartridge-containing supplementary electronic circuitry, and a pair of hand controllers for providing player control inputs to the console electronics. Improved connector apparatus is associated with the chute mechanism to enable electrical connection to be made to a cartridge contained printed circuit board with a minimum of insertion force.
    Type: Grant
    Filed: November 26, 1976
    Date of Patent: October 5, 1982
    Assignee: Fairchild Camera & Instrument Corp.
    Inventor: Ronald A. Smith
  • Patent number: 4346680
    Abstract: In an apparatus having a rotatable shaft supported by bearing members in a housing wherein said bearing members are suspended above an oil bath from which oil is splashed on said housing, an improvement for lubricating the bearing members comprising a method and means for admitting oil splashed from said bath on said housing through a wall of said housing to said shaft in the vicinity of said bearing members.
    Type: Grant
    Filed: June 19, 1980
    Date of Patent: August 31, 1982
    Inventor: Zenovie Boychuk
  • Patent number: 4335457
    Abstract: Semiconductor memory devices are tested by using a special purpose computer which uses simple test patterns to determine the weakest bits of the device and then tests only these relatively few "weak bits" and structurally and operationally adjacent bits using highly complex test patterns to determine if the device is functioning properly. This procedure considerably reduces testing time over that required using prior art techniques.
    Type: Grant
    Filed: August 8, 1980
    Date of Patent: June 15, 1982
    Assignee: Fairchild Camera & Instrument Corp.
    Inventor: James M. Early
  • Patent number: 4334157
    Abstract: A data latch of the kind having at least two operative modes, a transmitting or transparent mode or condition for transmitting data signals through the latch, and a latching mode or condition for latching and temporary storage by feedback of data signals in the latch. According to the invention there is provided in the data latch a pregate for pregating feedback signals in the latch. The pregate is adapted and coupled to provide positive feedback data signals for reinforcing previously entered data in the latching mode, and gating signals for passing input data in the transmitting mode.
    Type: Grant
    Filed: February 22, 1980
    Date of Patent: June 8, 1982
    Assignee: Fairchild Camera and Instrument Corp.
    Inventor: David A. Ferris
  • Patent number: 4330723
    Abstract: A transistor logic output device is provided with an active element discharging transistor coupled between the base of the pulldown element transistor and ground or low potential for actively controlling a route to ground or low potential for diverting and discharging the so-called capacitive feedback Miller current generated during the low to high potential transition at the output of the device resulting from base-collector junction capacitance in the pulldown element transistor. The active element discharging transistor is controlled at its base by the potential at the collector of the phase splitter element and is coupled to follow changes in voltage at the phase splitter collector for receiving base drive current during the transition from low to high potential at the device output and when the phase splitter is not conducting.
    Type: Grant
    Filed: August 13, 1979
    Date of Patent: May 18, 1982
    Assignee: Fairchild Camera and Instrument Corporation
    Inventor: Paul J. Griffith
  • Patent number: 4326270
    Abstract: An electronic circuit for simultaneously erasing all the information stored in an electronic information storage device and entering a predetermined new pattern of information into the storage device comprises a plurality of bistable semiconductor cells with an additional transistor current-conducting region included on a predetermined side of each cell. The additional current-conducting regions in the cells along each word row are coupled to an additional word line which connects to a current switch for the row. At an appropriate pulse signal, the current switch activates to switch row current temporarily from the standard current-source word line, which conducts holding current to the row during normal operation, to the additional word line, thereby erasing the old data and entering the new information bits.
    Type: Grant
    Filed: July 19, 1979
    Date of Patent: April 20, 1982
    Assignee: Fairchild Camera and Instrument Corp.
    Inventors: William K. Owens, Steven R. Kahermanes
  • Patent number: 4324216
    Abstract: An electronic advance and ignition control system incorporating the advance utilizes a fixed advance threshold compared with amplitude of an RPM sensitive input waveform from a distributor in combination with a timing circuit, which establishes a predetermined RPM rate above which the advance operates. The electronic advance accurately duplicates the function of conventional centrifugal and vacuum and advance retard mechanisms in controlling timing of an ignition coil drive signal. The electronic advance is provided as part of an ignition control integrated circuit which can operate in a stand alone mode or share control of the ignition system with a microprocessor through interface circuits also forming part of the integrated circuit.
    Type: Grant
    Filed: January 9, 1980
    Date of Patent: April 13, 1982
    Assignee: Fairchild Camera & Instrument Corp.
    Inventors: Nicky M. Johnson, Lawrence M. Blaser
  • Patent number: 4321533
    Abstract: A printed circuit board test fixture having interchangeable top plates (card personalizers). The test fixture is provided with a vacuum well having a field of probes mounted therein. The field of probes corresponds to the sum of all test points of a family of different printed circuit boards. Only a portion of all the probes are necessary to test any particular type of circuit board of the family. The top plate for each type of circuit board in the family has holes drilled completely therethrough only at locations where selected probes must pass through the top plate in order to contact the test points on the circuit board. In a preferred form, each top plate is partially drilled therethrough to form sockets at locations corresponding to the remaining probes which need not contact a particular circuit board. A hinged cover is provided for the vacuum well to allow easy removal and insertion of top plates.
    Type: Grant
    Filed: December 8, 1980
    Date of Patent: March 23, 1982
    Assignee: Fairchild Camera & Instrument Corp.
    Inventor: John L. Matrone
  • Patent number: 4316102
    Abstract: In a bias circuit including at least a pair of bipolar transistors interconnected to function as active loads, two junction field effect transistors are interconnected such that the source of one transistor is connected to the emitter of the first of the pair of bipolar transistors and the source of the second junction field effect transistor is connected to the emitter of the second of said bipolar transistors, and the gate electrodes of the first and second junction field effect transistors are electrically connected to each other and to the drain electrodes of both the first and second junction field effect transistors. Alternatively, the drain electrodes of the first and second junction field effect transistors are connected to a common bus and the gate electrodes are connected to a low impedance node.
    Type: Grant
    Filed: September 13, 1979
    Date of Patent: February 16, 1982
    Assignee: Fairchild Camera and Instrument Corp.
    Inventor: James R. Butler