Patents Represented by Attorney, Agent or Law Firm Whitham, Curtis, Whitham & McGinn
  • Patent number: 6194552
    Abstract: The antitope of an antibody is masked with a masking agent, followed by immobilization on a support. The masking agent is then eluted to produce an improved immunosorbent, which is capable of binding more than double the amount of an antigen than existing immunosorbents having the same antibody bound at the same density. Preferably, the masking agent is an antigen or other compound having an epitope for which the antitope of the bound antibody has an avidity. In a preferred embodiment, greater than 30% of the bound antibodies maintain the same vicinity as when unbound for specific antigen or hapten molecules. Preferably, the support is formed of any conventional immunosorbent support material which allows the bound and unbound antibody to maintain an avidity for the same compounds or antigens.
    Type: Grant
    Filed: August 19, 1994
    Date of Patent: February 27, 2001
    Assignee: Center for Innovative Technology
    Inventors: William H. Velander, Carolyn Orthner
  • Patent number: 5883812
    Abstract: An interconnection routing method for an intergrated circuit is applied to a channel area. The method includes the steps of calculating the length of each net in a given routing to thereby obtain a first set of nets having a long trunk. The nets in the first set are assigined to tracks in a central portion of the channel area to reduce crossings between the long trunk nets and other nets. The method further includes forming a second set for net pairs each running parallel in a long length with a small space therebetween. One of the net pairs in the second set is divided or doglegged to obtain a reduced coupled capacitance and crosstalk between the pairs. The present invention reduces crosstalk and coupled capacitance induced between parallel running interconnections or crossing interconnections.
    Type: Grant
    Filed: September 27, 1995
    Date of Patent: March 16, 1999
    Assignee: NEC Corporation
    Inventor: Takashi Fujii
  • Patent number: 5856026
    Abstract: A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH.sub.4 gas followed by WF.sub.6 can be used to produce an in-situ hard cap of W.sub.x Ge.sub.y. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450.degree. C.) without degrading the underlying metals.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: January 5, 1999
    Assignee: International Business Machines Corporation
    Inventors: Rajiv Vasant Joshi, Manu Jamnadaf Tejwani, Kris Venkatraman Srikrishnan
  • Patent number: 5840834
    Abstract: Two amino acid sequences are joined together using an electron acceptor moiety and a linking moiety, such as a chelating agent. In particular, an amino acid sequence specific for binding to a material interest is linked to an enzyme which acts on an indicator, such as a colorimetric, phosphometric, fluorometric or chemiluminescent substrate. The linking composition is useful in immunoassays.
    Type: Grant
    Filed: December 21, 1994
    Date of Patent: November 24, 1998
    Assignee: Virginia Commonwealth University
    Inventor: Darrell Peterson
  • Patent number: 5834361
    Abstract: In a method of forming a II-VI compound semiconductor thin film on an InP substrate, a layer of III-V compound semiconductor mixed crystal is first formed on the InP substrate. The desorption rate of a group V element constituting the III-V compound semiconductor mixed crystal at a decomposition temperature of a native oxide layer formed on a surface of the III-V compound semiconductor mixed crystal layer is lower than a desorption rate of P of the InP substrate at a decomposition temperature of a native oxide layer formed on a surface of the InP substrate. A II-VI compound semiconductor thin film layer is formed on the first III-V compound semiconductor mixed crystal layer.
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: November 10, 1998
    Assignee: NEC Corporation
    Inventors: Kouichi Naniwae, Toru Suzuki
  • Patent number: 5824580
    Abstract: A Field Effect Transistor (FET) and a method of forming FETs on a silicon wafer. First, trenches are formed in a surface of the silicon wafer. An ONO layer is formed on the surface, lining the trenches. Potassium is diffused along the ONO layer. Part of the ONO layer is removed to expose the wafer surface with the ONO layer remaining in the trenches. A gate oxide is formed on the exposed wafer surface. Finally, FET gates are formed on the gate oxide. Preferably, potassium is introduced during Chem-Mech polish when the trenches are filled with polysilicon. A slurry containing KOH is used to polish the polysilicon and the potassium diffuses from the slurry along the ONO layer. After Chem-Mech polish, the poly in the trenches is recessed by Reactive Ion Etching (RIE) it below the wafer surface. Optionally, after RIE, the wafer may be dipped in a KOH solution. Next, an oxide collar is formed along the ONO layer in the trenches above the recessed polysilicon.
    Type: Grant
    Filed: July 30, 1996
    Date of Patent: October 20, 1998
    Assignees: International Business Machines Corporation, Siemens Aktiengesellschaft
    Inventors: Manfred Hauf, Max G. Levy, Victor Ray Nastasi
  • Patent number: 5826078
    Abstract: A job re-execution system includes a status output controller for outputting a process status listing of each job, to an output unit. The processes to be re-executed are selected with an input unit. A process controller controls a processor to execute the processes. The processes to be re-executed are also selected by a re-execution controller.
    Type: Grant
    Filed: February 12, 1996
    Date of Patent: October 20, 1998
    Assignee: NEC Corporation
    Inventor: Tamio Funaki
  • Patent number: 5821586
    Abstract: A semiconductor device has a vertical MOS FET and a trigger element connected between the drain and the gate of the MOS FET. The trigger element has a heavily doped n region, a lightly doped p region and a lightly doped n region. The trigger element has a breakdown voltage lower than the drain-to-source rated voltage of the MOS FET and exhibits a negative resistance characteristic. A surge voltage enterring the drain of the MOS FET raises the gate potential of the MOS FET by flowing through the trigger element to thereby trigger the source-drain path of the MOS FET. The negative resistance characteristic of the trigger element enables to lower the temperature rise of the MOS FET to thereby protect the MOS FET against thermal destruction. A bidirectional diode set may be connected in series to the trigger element to design various breakdown voltage of the protective path.
    Type: Grant
    Filed: October 13, 1995
    Date of Patent: October 13, 1998
    Assignee: NEC Corporation
    Inventors: Kazumi Yamaguchi, Takao Arai
  • Patent number: 5815919
    Abstract: To prevent solder bridges that will easily occur in soldering an element whose leads are narrow in spacing. In a solder resist, there is provided an excess-solder absorbing region in which solder resist is not provided, between an end of a solder pad and the distal end of a lead. When a great deal of solder paste is applied to the solder pad for soldering the lead, an excess of solder melted due to the heat of a heater, flows along the lead and into the excess-solder absorbing region toward the distal end of the lead. Since the excess of solder does not flow across the solder resist provided between the leads, no solder bridge is formed.
    Type: Grant
    Filed: August 3, 1995
    Date of Patent: October 6, 1998
    Assignee: International Business Machines Corporation
    Inventors: Tohru Nakanishi, Hideo Ohkuma
  • Patent number: 5814210
    Abstract: A method and apparatus are disclosed for the microbubble flotation separation of very fine and coarse particles, especially coal and minerals, so as to produce high purity and high recovery efficiency. This is accomplished through the use of a flotation column, microbubbles, recycling of the flotation pulp, and countercurrent wash water to gently wash the froth. Also disclosed are unique processes and apparatus for generating microbubbles for flotation in a highly efficient and inexpensive manner using either a porous tube or in-line static generators.
    Type: Grant
    Filed: April 30, 1996
    Date of Patent: September 29, 1998
    Assignee: Virginia Tech Intellectual Properties, Inc.
    Inventors: Roe-Hoan Yoon, Gregory T. Adel, Gerald H. Luttrell
  • Patent number: 5812002
    Abstract: In a latching circuit including a first inverter having first input and output sides, a second inverter having second input and output sides, the first input side is connected to an input terminal, the second input side is connected to the first output side, the second output side is connected to the input terminal, and the second inverter further has first and second transistors having a primary conduction-type and are serially connected between first power supply terminal and the input terminal and including first and second gates having first and second gate lengths, respectively, third and fourth transistors having a secondary conduction-type reverse to the primary conduction-type and are serially connected between a second power supply terminal and the input terminal and including third and fourth gates having third and fourth gate lengths, respectively. The first gate length is greater than the second gate length while the third gate length is greater than the fourth gate length.
    Type: Grant
    Filed: June 14, 1996
    Date of Patent: September 22, 1998
    Assignee: NEC Corporation
    Inventor: Makoto Yoshida
  • Patent number: 5809535
    Abstract: A cache memory control apparatus for a cache memory having a data memory, includes an address array, a valid bit register, a comparator, and a dual-purpose register. The dual-purpose register stores one of a valid bit and a part of an address tag. The cache memory control apparatus applies to both a standard system with a plurality of blocks-per-line and a subordinate system with one block-per-line.
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: September 15, 1998
    Assignee: NEC Corporation
    Inventor: Takahiro Tanioka
  • Patent number: 5808927
    Abstract: A parallel multiply accumulator that provides a two's complement and unsigned multiply has a accumulator structure that minimizes the local and global interconnect lengths so that the design readily scales with advanced complementary metal oxide semiconductor (CMOS) integrated circuit (IC) technologies. The multiplier accumulator is formed with a plurality of identical panels, four in the preferred embodiment. Each identical panel implements the unique compensation necessary to form a multiplication/accumulation. The improved panel design is intended to operate in multiple panel designs and achieves a significant performance improvement. The improved multiply accumulator panel compensation is utilized for both two's complement compensation and according to the position of the panel within the overall array structure. Netlist generators are used to compile the netlist for both the main panel and the full adder arrays to sum the panels.
    Type: Grant
    Filed: October 18, 1994
    Date of Patent: September 15, 1998
    Assignee: International Business Machines Corporation
    Inventor: James Henry Hesson
  • Patent number: 5805846
    Abstract: A method for dynamically sharing an application in a conference system while maintaining state regardless of whether the application is under execution in all conference devices. The conference system includes a plurality of conference devices with at least one conference device executing an application program.
    Type: Grant
    Filed: November 21, 1996
    Date of Patent: September 8, 1998
    Assignee: International Business Machines Corporation
    Inventors: Amane Nakajima, Makoto Kobayashi, Fumio Ando
  • Patent number: 5805267
    Abstract: Eye-wear, such as eye glasses or goggles, are provided with lenses having an embedded fiber optic or optical waveguide mesh to produce an interactive light field (ILF) at the back of the wearer's eye. In order for the subject to see clearly through the glasses, controlled light enters from the periphery of the pupil, at an angle, such that the main image (i.e., the external environment scene) enters perpendicular to the pupil. The ILF tracks the pupil using the embedded fiber optic mesh. The wearer's brain is stimulated to adjust or maintain a circadian sleep rhythm despite natural light influences. The device has application for example in mitigating the effects of jet-lag, sleep disorders or helping shift workers adjust to a new shift.
    Type: Grant
    Filed: June 13, 1996
    Date of Patent: September 8, 1998
    Inventor: Neil Goldman
  • Patent number: 5805917
    Abstract: A parallel processing system includes a plurality of processors, a plurality of communication register modules each including a communication register, and an interconnecting network for connecting the plurality of processors and the plurality of communication register modules. The interconnecting network receives and simultaneously transmits first and second accesses from first and second processors of the plurality of processors to first and second communication register modules of the plurality of communication register modules, respectively. Each of the plurality of communication register modules may include a communication register set. The communication register set includes the communication register. The communication register set may include a lock bit. Each of the plurality of communication register modules may include a test and set part.
    Type: Grant
    Filed: June 13, 1995
    Date of Patent: September 8, 1998
    Assignee: NEC Corporation
    Inventors: Keiko Sakurada, Noriyuki Ando
  • Patent number: 5798525
    Abstract: Structures having high height to width ratios may be measured using X-ray techniques, where the surrounding base and the structure are composed of different substances. The technique combines X-ray detection with scanning electron microscope (SEM) beam scanning. The X-ray emission is set to detect the presence of a specific substance which is either in the structure or surrounding the structure.
    Type: Grant
    Filed: June 26, 1996
    Date of Patent: August 25, 1998
    Assignee: International Business Machines Corporation
    Inventors: Peter Benizri-Carl, Wolfgang Egert, Manfred Jung, Theodore Gerard van Kessel
  • Patent number: 5799019
    Abstract: A circuit for converting frame data is disclosed, in which data communications can be carried out by matching the T1 repeater line of the North American method and the E1 repeater line of the CEPT. The four 32-channel frame data of the E1 line of the CEPT method are converted into parallel data of 8-bit one channel, and are stored into four 64-byte buffers. The stored 32-channel frame data are read out by 24 channels at a time, while the remaining data of the 6 channels are added to the data which have been stored in the buffers. Thus five 24-channel frame data are converted into serial data before being outputted. Of the five 24-channel frame data of the T1 repeater line of the North American method, four 24-channel frame data are stored into four 64-byte buffers, while the remaining one 24-channel frame data are separated by 6 so as to store them into the four 64-byte buffers, so that the four 64-byte buffers can store the 32-channel data respectively.
    Type: Grant
    Filed: June 14, 1996
    Date of Patent: August 25, 1998
    Assignee: Hyundai Electronics Ind. Co., Ltd.
    Inventors: Young-Goo Kim, Sung-Dong Kim
  • Patent number: 5792596
    Abstract: In a method of forming a pattern, a photo-mask including a desired pattern is provided. A photo-sensitive resin film is spin-coated on a semiconductor substrate. Subsequently, the surface of the photo-sensitive resin film is changed to have a resistivity against a development solution. Next, light is illuminated to transmit the photo-mask. As a result, the resistivity of only the surface portion of the photo-sensitive resin film corresponding to the desired pattern is decreased based on the property of photo-sensitive resin film by the light having transmitted the photo-mask. Last, the photo-sensitive layer is developed with the development solution.
    Type: Grant
    Filed: February 6, 1996
    Date of Patent: August 11, 1998
    Assignee: NEC Corporation
    Inventors: Tadao Yasuzato, Shinji Ishida, Kunihiko Kasama, Yoko Iwabuchi
  • Patent number: D397723
    Type: Grant
    Filed: September 3, 1997
    Date of Patent: September 1, 1998
    Assignee: Kotobuki & Co., Ltd.
    Inventor: Hiromichi Izushima