Abstract: A motion detecting circuit and a noise reducing circuit of high reliability and independent of the magnitude of motion, presence/absence of noise, and magnitude of the noise. The motion detecting circuit includes a subtractor 14 which receives as inputs, an input video signal VS.sub.i from an input terminal 10 and a delayed video signal VS.sub.d delayed by one picture unit (one frame in the case of the NTSC format) from a frame memory 12. The difference between the two signals VS.sub.i and VS.sub.d is taken and a difference signal e is output for each pixel of a video display.

Abstract: A semiconductor memory device and an initialization method therefor, wherein writing of the initialization data into memory cells of the semiconductor memory device can be performed in a simple way in a short period of time. When initialization is performed, a high (H) level initialization mode signal DFT is generated from initialization control unit 24. A sense amplifier driving circuit 20 sets a sense amplifier driving signal PC, NC to the high-impedance state, equalization control signal generating unit 22 maintains the equalization control signal .phi.E on the H-level, and bit line driving circuit 26 sets precharge feed line BLR on Vcc (H-level) or Vss low (L) level). In this way, in the memory cell array, the operation of sense amplifier SAi of each row stops, and transistors TR3, TR4, TR5 of precharge circuit PRi are ON, while voltage Vcc or Vss of precharge feed line BLR is fed to two bit lines BLi, BLi- through transistors TR1, TR2. In this state, the word line WLj of the assigned column is activated.

Abstract: A first silicon controlled rectifier structure (220) is provided for electrostatic discharge protection, comprising a lightly doped semiconductor layer (222) having a first conductivity type and a face. A lightly doped region (224) having a second conductivity type opposite the first conductivity type is formed in the semiconductor layer (222) at the face. A first heavily doped region (226) having the second conductivity type is formed laterally within the semiconductor layer (222) at the face and is electrically coupled to a first node (62). A second heavily doped region (230) having the second conductivity type is formed laterally within the lightly doped region (224) and is electrically coupled to a second node (58). A third heavily doped region (228) having the first conductivity type is formed laterally within the lightly doped region (224) to be interposed between the first and second heavily doped regions (226 and 230) and is electrically coupled to the second node (58).

Abstract: A process variance detection technique for detecting fabrication processing variances in integrated circuit components, such as resistors or MOSFETs, is based on the decreased sensitivity to processing variations exhibited by components that are up-sized relative to similar components with nominal dimensions. Detection circuitry includes detection components with both nominal and up-sized dimensions, and variance detection involves detecting the differences in operational response of the nominal and up-sized detection components. For bipolar logic, resistors are fabricated with up-sized widths, while for MOS logic, MOSFETs are fabricated with up-sized gate lengths.

Abstract: An arrangement for monitoring the operating state of vehicle pneumatic tires (14) mounted on wheel rims (10) is provided with sensors (40, 42) for detecting the air pressure and the air temperature in each tire. Furthermore, it includes transmitting means comprising rim-side mounted rotor members (28) and bodywork-side mounted stator members (32) coupled thereto for transmitting the parameters detected by the sensor (40, 42) to an evaluating arrangement in the vehicle connected to the stator members. The pressure sensor (40) and the temperature sensor (42) of each tire (14) are coupled to a first transponder (44) which as reaction to an interrogation signal generated by the evaluating arrangement transmits the data supplied to it by the pressure sensor (40) and the temperature sensor (42) to the rotor members (28) of the transmitting means.

Abstract: A method for optimizing a circuit containing a finite state machine (FSM) based on transition density. A first state assignment is assigned for each state. Then, a first transition density characteristic associated with the first state assignment is determined and a second state assignment, different from said first state assignment is assigned for each state. A second transition density characteristic associated with the second state assignment is then determined and the first state assignment is set equal to the second state assignment if second transition density characteristic is less than a predetermined amount. The process is repeated until the transition density has been minimized.

Abstract: A semiconductor device comprises a piezoresistive pressure sensor (12), which has a membrane (14), which is constituted by a conducting epitaxy layer (16), which is applied to a conducting semiconductor substrate (18) of the opposite conductivity. On the outer surface (20) of the membrane facing away from the semiconductor substrate (18) at least one piezoresistor (22) is incorporated. Between the semiconductor substrate (18) and the epitaxy layer (16) an annularly structured intermediate layer (28) is incorporated, which defines a region (26'), adjoining the inner surface (24) of the membrane, of an opening (26) extending through the semiconductor substrate (18). This opening (26) is produced by anisotropic semiconductor etching, the intermediate layer (28) having a conductivity which is opposite to that of the semiconductor substrate so that this intermediate layer (28) functions as an etch stopping means and is not attacked by the etchant.

Abstract: A method for planarizing the surface of a layer in a semiconductor device includes forming conductor regions 24, 26, and 28 on a layer of the semiconductor device; forming first insulator regions 30, 32, and 34 in gaps between the conductor regions 24, 26, and 28; and forming an insulator layer 40 over the first insulator regions 30, 32, and 34, and over the conductor regions 24, 26, and 28 such that a surface of the insulator layer 40 will be substantially planar.

Abstract: An 8-input, 1-output mux-based logic module for an FPGA is disclosed. The logic module comprises five separate multiplexers connected differently in the various embodiments of the present invention. The 8-input logic module can realize a total of 2390 unique functions. A 7-input, 1-output variation of the logic module of the preferred embodiment is also disclosed.

Abstract: A BiCMOS device 10 having a bipolar transistor 60, a PMOS transistor 64 and a p-type polysilicon resistor 70. Bipolar transistor 60 is comprised of an emitter electrode 30, base region 26, and collector region formed by well region 18. PMOS transistor 64 comprises source/drain regions 52, gate electrode 40, and gate oxide 28. PMOS transistor 64 may also comprises LDD regions 44. The emitter electrode 30 and gates 40 are formed out of the same polysilicon layer and thus have the same thickness. If desired, the emitter electrode 30 and gate electrodes 40 may be silicided.

Abstract: Circuitry (10) and structures (30) are provided for electrostatic discharge protection. A first bipolar transistor (Q1) has a collector electrically coupled to a first node (12), a base electrically coupled to a second node, and an emitter electrically coupled to a third node (14). A second bipolar transistor (Q2) has a collector, a base electrically coupled to the second node, and an emitter electrically coupled to the first node (14). The second bipolar transistor (Q2) supplies a base current to the base of the first bipolar transistor (Q1) in response to the first node (12) reaching a threshold voltage relative to the third node (14), so that the first bipolar transistor (Q1) conducts current between the first (12) and third (14) nodes in response to the base current.

Abstract: The circuit for generating current has a controllable current source M.sub.7, an input transistor pair 24 having a first branch and a second branch, a current mirror 28 having a first branch and a second branch, and an amplifier 50. The controllable current source M.sub.7 is coupled to the first and second branches of the input transistor pair 24. The first branch of the current mirror 28 is coupled to the first branch of the input transistor pair 24. The second branch of the current mirror 28 is coupled to the second branch of the input transistor pair 24. The input transistor pair 24 is coupled between the controllable current source M.sub.7 and the current mirror 28. The amplifier 50 has an output coupled to the controllable current source M.sub.7, and a first input coupled to the second branch of the input transistor pair 24 and the second branch of the current mirror 28.

Abstract: An integrated circuit having a plurality of modules and an internal communication bus interconnecting the modules is arranged to produce an output indicating which module is granted access to the bus at the time. A control means grants to a module access to the bus in response to a request from the module on the basis of the priority of its request amongst any other requests for access. The control means produces the output indication in digital form which is multiplexed with other data from the bus at an output port of the integrated circuit.

Abstract: Video graphics display system having a display adapter connected between a host processor (2) and a display unit (6). The display adapter includes a video memory (4) which has first and second memory parts (3) and (8). A graphics processor (1) is connected between the host processor and the first memory part (3) of the video memory (4) which is operably connected to the display unit. The second memory part (8) of the video memory (4) is connected to a logic based hardware sub-system (7), the logic based hardware sub-system being further connected to the host processor. The host processor effectively provides software and hardware compatible applications associated with the graphics processor and the logic based hardware sub-system for implementation as display data stored in the first and second memory parts of the video memory. The display unit may provide a display based upon the memory content of either the first or the second memory part of the video memory, or a combination of both memory parts.

Abstract: A bipolar transistor (100) and a method for forming the same. A base-link diffusion source layer (118) is formed over a portion of the collector region (102). The base-link diffusion source layer (118) comprises a material that is capable of being used as a dopant source and is capable of being etched selectively with respect to silicon. A barrier layer (119) is formed over the base-link diffusion source layer (118). A base electrode (114) is formed over at least one end portion of the barrier layer (119) and base-link diffusion source layer (118) and the exposed portions of the barrier layer (119) and underlying base-link diffusion source layer (118) are removed. An extrinsic base region (110) is diffused from the base electrode (114) and a base link-up region (112) is diffused from the base-link diffusion source layer (118). Processing may then continue to form an intrinsic base region (108), emitter region (126), and emitter electrode (124).

Abstract: The charge coupled device cell has a semiconductor layer 20 of a first conductivity type, a buried channel 22 of a second conductivity type on the semiconductor layer 20, a first virtual gate 24 in the buried channel 22, the first virtual gate is switched between at least two potential levels, and a first bipolar gate 42 in the buried channel 22 adjacent the first virtual gate 24.

Abstract: A logic module uses a multiplexer which can be used to configure the logic module as combinational or sequential. A sequential block comprises a flip-flop with preset and clear, and can be SR or D-type. The multiplexer is used in the feedback loop of the flip-flop, thus by choosing an appropriate select signal the feedback can be connected/disconnected.

Abstract: An active memory 14 is provided which includes a data memory 20 including rows and columns of storage locations for holding data and computational results. A broadcast memory 22 includes rows and columns of storage locations for holding control instructions. Computing circuitry 26 is provided which is operable to perform a first computational operation using first and second words of data retrieved from the data memory 20 and perform a second computational operation using a result from the first operation and a result from a previous operation. Control circuitry 24 is operable in response to control instructions received from broadcast memory 22 to control the transfer of the first and second words of data from the data memory 20 to said computing circuitry 26 and the performance of the first and second operations.

Abstract: An image sensor element having at least one charge storage well 70 and 80, charge transfer structures for transferring charge from one charge storage well 70 to another charge storage well 80, and a charge sensor for sensing charge levels in a charge storage well 70 without removing the charge from the well. Other devices, systems and methods are also disclosed.

Abstract: A semiconductor integrated circuit comprising a MOSFET having a metal wiring layer formed via an insulating film above and along the gate electrode of the MOSFET. The MOSFET is structured such that its channel length is small or channel width is large, and an input signal is applied from at least both end sides of the gate electrode thereof. Since the metal wiring layer for the input signal is formed on the gate electrode of the MOSFET, high-speed operation is possible without increasing the layout area. FIG. 1.