Abstract: Data in a system having dynamic random access memories (DRAM's) is preserved despite loss of the primary source of electrical power to that system. A Flash RAM and a small auxiliary power source are employed by a controller independent of the system to transfer the DRAM contents to the Flash RAM immediately upon loss of primary system power. The data is also automatically returned to the DRAM after return of primary power with special data signals or sequences being utilized in a multiple controller environment so as to award the complete data recovery function to the first controller to demand attention.

Abstract: A RAID-compatible data storage system which allows incremental increases in storage capacity at a cost that is proportional to the increase in capacity. The system does not require changes to the host system. The control and interface functions previously performed by a single (or redundant) central data storage device controller are distributed among a number of modular control units (MCUs). Each MCU is preferably physically coupled to a data storage device to form a basic, low-cost integrated storage node. One of two bus ports interfaces an MCU with the host computer on a host bus, and the other bus port interfaces an MCU with one or more data storage devices coupled to the MCU by a data storage device bus. The serial interface ports provide a means by which each of the MCUs may communicate with each other MCU to facilitate the implementation of a memory array architecture.

Abstract: A method and apparatus for removing a virtual connection between first and second devices in a communication system that includes at least one switch virtually connecting the first and second devices. An error in the virtual connection can be detected in at least one of the first and second devices and the at least one switch, with the detector transmitting a request to remove the virtual connection. The virtual connection then is removed from the communication system in response to the transmission of the request. The request to remove the virtual circuit may be in the form of an information frame transmitted over the virtual connection, with each system component being removed from the virtual circuit upon its processing of the information frame. Additionally, a method and apparatus for operating the virtual connection between the first and second devices.

Abstract: A system and method for mitigating undesired imprint effects in a ferroelectric memory array through the addition of a complementary data path which allows user data to be written to the array in an inverted state and then subsequently read out from the array in a re-inverted state in response to the state of at least one indicator bit corresponding to each row of the array.

Abstract: An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address.

Abstract: An enhanced dynamic random access memory (DRAM) contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at static random access memory (SRAM) speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address.

Abstract: A system and method for data entry and retroactive reconstruction of the relative position of features and objects, in particular with respect to scenes such as transitory occurrences, utilizing a signal transmitting and receiving distance determining device. In a particular embodiment, the system and method disclosed has especial applicability to the on-scene recordation and subsequent ex post facto reconstruction of traffic accident scenes by law enforcement officers and may be readily and efficiently implemented in conjunction with a commercially available laser-based speed and distance determining device otherwise usable for vehicle speed traffic monitoring functions utilizing either triangulation or baseline/offset mensuration techniques.