Abstract: A programmable logic array is constructed of independently controllable logic building blocks of two types and special output logic to perform desired logic functions. The first building block is a functional element which is capable of performing any logical function of its input data to create output data. The functional elements shown are based on three inputs with a single output. The second basic type of building block is a pass-through/hold device which may either pass its input directly through as an output, or which may latch and hold the input until clocked. A plurality of logic levels or ranks of elements of the first type and ranks of the second type are interconnected so that the output can be various functions of the inputs. The logic array described here has first and second logic levels consisting of functional elements followed by a third level of pass-through/hold devices. The fourth and fifth logic levels are functional elements and pass-through/hold devices.

Abstract: A memory organization for holding memory refresh data for a display uses input address selectors for memory modules for a segmented display to provide horizontal rotation of all data in the memory modules. On writing of vertical vectors, a logic tree using Exclusive ORs modifies memory address bits to provide tilt to the vertical vector and cause it to be orthogonal to horizontal vectors. Output data selectors read data from the memory modules to the display and derotate the data so that the display is restored to its original form.

Abstract: The bit configurations are arranged in M-bit code words, each word comprising a number D of data bits and an even number N of error correcting bits. The data bits are partitioned into N fields with an error correcting bit associated with each field to indicate the parity of the associated field. The assignment of data bits to the N fields in such that, when the N fields are used to generate an N-bit error syndrome, this syndrome will contain an odd number n1 of bits at a first value if there is a single bit in error, where N-n1=n2 is also odd, and an even number of bits different from N to indicate a two-bit error. The number of bits of the first value are then used to determine whether the codeword is in its true or inverted form.

Abstract: An optical recording system has a system optical apparatus carried by a fine tracking system which moves the optical apparatus for small track seeking movements and for track following. The fine tracking system is carried by a linear actuator coarse tracking system which makes large track seeking movements so that the entire area of the optical recording media is available to the system. Both the coarse tracking system and the fine tracking system are operated by servo control loops. The fine tracking system responds to tracking status signals with respect to track following and track seeking signals in response to track addressing information. The coarse tracking system responds to position sensor signals derived from a position sensor which is associated with the fine tracking system and provides signals related to the relative position of the fine tracking system to the coarse tracking system.

Abstract: A digital storage includes several sections having different time characteristics. Such sections are operated in the overlap mode and include a common address and control circuit. The fast sections store data which are accessed more frequently or which are addressed first when data blocks are transferred. The digital storage may be used in a storage hierarchy comprising a cache storage and wherein only data blocks positioned at main storage address boundaries are transferred to the cache storage.

Abstract: In a bubble memory package, a contoured, shaped magnet and filler plate combination is provided to shape the magnetic field in a uniform fashion to prevent the loss of magnetic flux density which normally tends to occur in the center of the magnet area of a planar, uniformly thick magnet.

Abstract: A microcode control memory having a first memory for receiving initial instructions is shown in combination with at least one additional memory for executing multistep control functions in a computer system. The first memory receives all initial control instructions from an instruction stack and produces the appropriate control output. Simultaneously as part of the initial instruction, a memory select network receives a control bit so that an output select network connected to the output of all memories passes the output from the first memory to the output register. Single step instructions are processed continuously this way. Multistep instructions are performed by using a portion of the output from the first memory to serve as the address selection in one of the other memories. When a multistep instruction is completed, the output select network again selects the output from the first memory for gating to the output register.

Abstract: A cache memory organization is shown using a miss information collection and manipulation system to insure the transparency of cache misses. This system makes use of the fact that the cache memory has a faster rate of operation than the rate of operation of central memory. The cache memory consists of a set-associative cache section consisting of tag arrays and control with a cache buffer, a central memory interface block consisting of a memory requester and memory receiver together with miss information holding registers section consisting of a miss comparator and status collection device. The miss information holding register section allows for an almost continual stream of new requests for data to be supplied to the cache memory at the cache hit rate throughput.

Abstract: A test system performs dynamic testing of complex logic modules at full system clock rates and is resident on each LSI chip under test. The system logic is designed to be included on each LSI chip to reduce the time and computation required to detect and isolate faults in systems built from one or more chips. The on chip system includes switchable transmission gates to alter logic paths, a control shift register in the test function, an input shift register, an associated test generator and accumulator, an output shift register and an associated generator and accumulator. This logic provides test operands for the logic function under test and analyzes the resultant operands. Test operands are produced using a shift register connected to all inputs of the logic function under test. Checksum logic together with a shift register produce a running checksum of all output states of the module under test at the operative clock rate of the LSI.

Abstract: A time synchronization system involves a master station sending time information to a remote station and in which a portion of the time message is used as a trigger to start a counter or interval clock in the remote station. When the time message is concluded, the remote station adds the time in the interval clock or counter to the time from the message received to create an actual time which replaces the existing time information in the remote station clock. The time portion of the message sent represents the actual time at which the trigger in the time message was actuated and represents a later portion of the message as sent.

Abstract: In a microcode control memory for a computer central processing unit, a network is provided for generating a modified microcode address in a sequence of instructions where the modified address is determined by a function of the results of preselected events.

Abstract: A temperature compensated current source includes three successive source current paths to produce a controlled output current. Each current path has a different value of current flowing therein so that current fluctuations in one current path will tend to be isolated from the other current paths because of the difference in current flow. In the embodiment of the invention shown, a reference zener diode provides a reference voltage at the base of a first transistor to establish a first reference current as its emitter current. A second transistor uses the first current as the reference to establish a second current value which has a positive temperature coefficient. Third, fourth and fifth transistors use the second reference current to establish a third reference current value independent of the gain values of these transistors.

Abstract: An ink jet printer is provided which will print in both the left to right and right to left directions of ink jet head travel with respect to the print media. Relative horizontal displacement of ink jet droplets caused by horizontal travel of the ink jet head is compensated for by a deflection plate system which is tilted with respect to the direction of travel to provide an electric field which tilts the pattern of ink jet droplets in an equal and opposite amount from that caused by horizontal movement of the ink jet head. In one direction of travel an ascending pattern of ink jet droplets is provided and in the other direction of travel a descending pattern of ink jet droplets is provided for printing so that the tilted deflection plate system compensates appropriately for the particular direction of travel.

Abstract: A high-speed binary divider is provided which produces two quotient bits per processor cycle using two carry-save adders in a nonrestoring division mode with a delayed sign logic circuit selecting the adder having the required adder result for the current partial remainder.

Abstract: A microcode addressing system is shown which has two modes of operation for different memory search functions. The first mode, the Slow mode in which the memory operates at a standard read rate, is the mode in which the computer central processing unit performs predetermined sequential tasks in a normal fashion. The second mode of operation is the Fast mode of operation in which the memory responds to unpredetermined, dynamically changing events in the computer system at a faster than standard cycle time in order to search for and identify a particular word in central memory.

Abstract: This invention uses a plurality of bubble memory chips in a system for providing simultaneous input and output in a word or byte organized output. Each bubble memory chip has the same number of minor loops as is required for nominal memory size without the requirement for extra or redundant loops. Each bubble memory chip may have a number of faulty minor loops where the bit output is incorrect and cannot be used. However, a requirement for this system is that no two bubble memory chips may have a faulty bit or minor loop at the same major loop address location. An additional bubble memory chip is provided which will contain the correct data bits for locations corresponding to defective major loop addresses in the bubble memory chips making up the byte. A Programmable Read Only Memory (PROM) is provided and connected with a logic network to control the gating of the outputs of the bubble memory chips associated with the memory byte and the extra bubble memory chip to control the gating of the outputs.

Abstract: This is a system for connecting flexible electrical connectors having raised conductors above an insulating substrate to a plasma display panel having a glass substrate with the electrical conductors deposited in the bottom surface of conductor pathways etched in a glass substrate. The raised conductors on the connectors mate with the depressed conductors in the panel substrate. The spacing of the conductors in the connector may be varied to facilitate an exact mating with the conductors in the panel substrate. A clip device in combination with a flexible insulating force spreading member applies a uniform continuous pressure to the connector cable and glass substrate combination to maintain connection. This system may be used to facilitate the direct attachment of large scale integrated circuit chip carriers having conductor members on a surface thereof directly to conductors in a plasma display panel substrate.

Abstract: A polynomial generator for use in an error code correction system consists of an input data multiplexer for determining the mode of operation, a plurality of polynomial enable gates to allow insertion of a predetermined polynomial, a plurality of check character generating gates divided into a first group and a second group for forming an output polynomial from the input data and the predetermined polynomial, an output holding register and a pair of decode gates for constantly monitoring the contents of the holding register to provide an indication of either of two particular conditions.

Abstract: A multiplier for use with polynomials in an error correction system wherein the multiplier and multiplicand are first encoded from m bits to N bits, where N is greater than m, and wherein the multiplication is accomplished on a bit basis by arrays of AND gates and where the resultant product is decoded from R bits to S bits where S is less than R.

Abstract: In a field access type bubble memory system using a major loop-minor loop organization, redundant loops are included in each memory chip so that defective minor loops may be disregarded and the memory retain its nominal capacity. Thus, the total number of loops is in excess of the nominal capacity. In one form of the invention the redundant loops are included with the minor loops. In another form of the invention, the redundant loops are independent of the minor loops. A stationary register or flaw chain having at least as many storage locations as the number of minor loops is located on the bubble memory chip with the major and minor loops. Each register location is assigned to contain information with respect to an assigned corresponding minor loop.