Abstract: An improved photoimagable cationically polymerizable epoxy based solder mask is provided that contains a non-brominated epoxy resin system and from about 0.1 to about 15 parts, by weight per 100 parts of resin system, of a cationic photoinitiator. The non-brominated epoxy-resin system has solids that are comprised of from about 10% to about 80% by weight, of a polyol resin having epoxy functionality; from about 0% to about 90% by weight of a polyepoxy resin; and from about 25% to about 85% by weight of a difunctional epoxy resin. The photosensitive cationically polymerizable epoxy based system is especially useful as a solder mask and does not contain bromine.

Abstract: An improved method of burn-in of I/C chips is provided wherein, at the beginning of the burn-in process, the thermal resistance between the heatsink and the chip is measured at reduced power, the maximum allowable thermal resistance between the chip and heatsink interface is calculated and compared to the actual thermal resistance of the interface. If the actual thermal resistance measured at the interface between the heatsink and the chip package is greater than the maximum allowable calculated thermal resistance, then the corrective action is initiated in order to prevent damage to the I/C chip during burn-in or increase efficient use of the test sites.

Abstract: The method for producing a printed wiring board comprising the steps of preparing a conductive substrate, forming an insulating layer on one surface of the said substrate, forming at least one via hole in the insulating layer, thermally curing the insulating layer, and reducing at least one oxidized layer formed on the other conductive surface of the substrate during the curing operation. Alternatively, the thermal cure may be accomplished in an atmosphere (e.g., reducing gas, inactive gas, or mixtures thereof) not conducive to oxide formation on metallized circuit surfaces.

Abstract: The electrical connections of an integrated circuit chip assembly comprised of an integrated circuit chip attached to a substrate are encapsulated and reinforced with a high viscosity encapsulant material by dispensing the encapsulant material through an opening in the substrate into the space between the integrated circuit chip and the substrate. An integrated circuit chin assembly having a reinforced electrical interconnection which is more resistant to weakening as a result of stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.

Abstract: An improved chip sparing system and method of operation are provided in which a failed chip is detected even if there are multiple errors on a single chip and one or more spare chips are provided within the system; and in which spare chips or space chip I/Os are dynamically inserted into the system upon detection of a failed chip or chip I/O without the necessity of shutting down and rebooting the system or even without the necessity of re-initializing the memory.

Abstract: A process for tenting through-holes comprises providing a circuitized substrate having a plurality of plated through-holes, wherein the plated through-holes are tented with a polyimide material.

Abstract: A molding device and method utilizes a cavity including first and second parts for molding an article having one or more convex portions and a gate for injecting mold resin into the cavity. The gate in turn includes one or more gate sides for injecting resin into a concave portion of one part and a gate base for injecting resin into a second of the parts in which no concave portions are located, both resin injections occurring simultaneously and substantially encapsulating a semiconductor element to form a molded article having a convex lens.

Abstract: A bandwidth conserving queue manager for a FIFO buffer is provided, preferably on an ASIC chip and preferably including separate DRAM storage that maintains a FIFO queue which can extend beyond the data storage space of the FIFO buffer to provide additional data storage space as needed. FIFO buffers are used on the ASIC chip to store and retrieve multiple queue entries. As long as the total size of the queue does not exceed the storage available in the buffers, no additional data storage is needed. However, when some predetermined amount of the buffer storage space in the FIFO buffers is exceeded, data are written to and read from the additional data storage, and preferably in packets which are of optimum size for maintaining peak performance of the data storage device and which are written to the data storage device in such a way that they are queued in a first-in, first-out (FIFO) sequence of addresses. Preferably, the data are written to and are read from the DRAM in burst mode.

Abstract: An improved structure and method of operation are provided wherein a single RAM (random access memory) can be serviced by two CAMs (content addressable memory). This is accomplished by providing first actuating circuitry operably associated with and operatively connecting a first CAM to a selected portion of the RAM and second actuating circuit associated with and operably connecting a second CAM to a second portion of the RAM. The first actuating circuitry includes circuitry to actuate a selected wordline responsive to a CAM search read and RAM search read and circuitry to initiate a CAMRAM index read and index write operably responsive to given control logic. The second circuitry includes circuitry to actuate a selected wordline responsive to a CAM search read and RAM search read responsive to given control logic.

Abstract: The electrical interconnections between an integrated circuit chip assembly are encapsulated and reinforced with a high viscosity encapsulant material in a single step molding process wherein a mold is placed over an integrated circuit chip assembly and encapsulant material is dispensed through an opening in the mold and forced around and under the integrated circuit chip by external pressure encapsulating the integrated circuit chip assembly. An integrated circuit chip assembly having a reinforced electrical connection which is more resistant to weakening as a result is stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.

Abstract: A printed circuit board comprises a base substrate including a conductive circuit pattern on a top surface thereof, and at least one photosensitive resin layer positioned on the base substrate. The resin layer exposure is performed through a photomask having light-shielding and exposure amount adjusting portions as part thereof to accommodate for varying resin layer thicknesses.

Abstract: A method for reactive ion etching of SiO2 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8.

Abstract: The present invention provides a new device and method for enhancing the electrical properties of the thick metal backer/electrically conductive thermoset adhesive/printed circuit board or card assembly. The enhanced electrical properties are obtained by providing a thin bondline of conductive adhesive that is essentially void free.

Abstract: A method for fabricating circuitized substrates which reduces shorts, and does not require baking and resulting film. The method employs a photoimageable dielectric film, having a solvent content less than about 5%, and a glass transition temperature, when cured, which is greater than about 110° C. A photoimageable dielectric film is provided having from about 95% to about 100% solids, and comprising: from 0% to about 30% of the solids, of a particulate rheology modifier; from about 70% to about 100% of the solids of an epoxy resin system (liquid at 20° C.) comprising: from about 85% to about 99.9% epoxy resins; and from about 0.1 to 15 parts of the total resin weight, a cationic photoinitiator; from 0 to about 5% solvent; applying the photoimageable dielectric film to a circuitized substrate; and exposing the film to actinic radiation.

Abstract: A method of making a circuitized substrate having plated through holes free of filler material is provided. The method includes the steps of providing a dielectric substrate having first and second opposite faces. At least one via hole is formed from one face to the other. A first electrically conductive layer is applied onto the top and bottom faces of the dielectric member and onto the side wall of the via. First layers of photoresist are applied to each layer of conductive material and entering at least partially into the via hole. The first layers of photoresist are selectively exposed and developed to remove all of the photoresist, except that photoresist which is disposed in the via holes. Thereafter, a portion of the faces of the metal coatings on the surfaces of dielectric material and any photoresist remaining in the holes extending above the layers of electrically conductive material are removed to form a planar surface thinner than the thickness of the metal in the through hole.

Abstract: A method of forming a core for and forming a composite wiring board. The core has an electrically conductive coating on at least one face of a dielectric substrate. At least one opening is formed through the substrate extending from one face to the other and through each conductive coating. An electrically conductive material is dispensed in each of the openings extending through the conducting coating. At least a portion of the surface of the conductive coating on one face is removed to allow a nub of the conductive material to extend above the substrate face and any remaining conductive material to thereby form a core that can be electrically joined face-to-face with a second core member or other circuitized structure.

Abstract: An improved memory card and its use in a computer system is provided. The computer system has a system bus which provides requests from a CPU to a memory controller, which then provides signals to the memory card or module or a memory bus. The memory card is provided with first and second banks of DRAMs, a memory card bus and a DSP. Logic circuitry including a memory card data bus controller provides communication of the DSP with the banks of DRAM chips. Logic circuitry is also provided which can selectively connect the DSP to either the first or second bank of DRAMs and selectively connect the memory bus with the other bank of DRAMs or with both banks of DRAMs. Hence when the CPU is accessing one bank of DRAMS the DSP can access the other bank of DRAMs thus allowing the DSP to function utilizing the bank of DRAMs not being accessed by the memory bus to service the CPU or some I/O device.

Abstract: A substrate and a method of making the substrate is provided. The substrate includes a layer of metal with at least one through hole therein, the layer of metal having an adhesion promoting layer thereon. A layer of a partially cured low-loss polymer or polymer precursor is positioned on the adhesion promoting layer and a plurality of conductive circuit lines are positioned on a portion of the partially cured dielectric layer. The substrate can be used as a building block in the fabrication of a multilayered printed circuit board.

Abstract: A memory card adapter and method is provided which can add features or provide functions to a computer system's memory modules without having to replace and discard existing memory modules. An adapter is provided which has electrical contacts that are capable of being plugged into a memory module receiving socket of. a motherboard and a memory module receiving socket capable of receiving and retaining a memory module such as a SIMM. The adapter has logic, circuitry and/or memory chips to add new function to the existing memory module and also has all information and hardware needed for proper interface with the motherboard of the computer system. The present invention can add a variety of function such as parity, error correction code and error correction code on SIMM as well as convert signals which form from the system for use on the SIMM which signals in the form generate by the computer are not compatible with the SIMM.

Abstract: High aspect ratio (5:1-30:1) and small (5 &mgr;m-125 &mgr;m) diameter holes in a dielectric substrate are provided, which are filled with a solidified conductive material, as well as a method of filling such holes using pressure and vacuum. In certain embodiments, the holes are lined with conductive material and/or capped with a conductive material. The invention also contemplates a chip carrier formed by such material.