Patents Represented by Attorney William Park & Associates Ltd.
  • Patent number: 8351282
    Abstract: A semiconductor memory apparatus includes a data input enable signal generation block configured to sequentially delay a data strobe signal to generate a first delayed data strobe signal, a second delayed data strobe signal, a third delayed data strobe signal and a fourth delayed data strobe signal, and generate a data strobe enable signal in response to a CAS write signal, a CAS write latency signal and the first to fourth delayed data strobe signals, a latch control signal generation block configured to output the data strobe signal as a latch control signal during an enable period of the data strobe enable signal, and a data latch block configured to latch data in response to the latch control signal and output latched data.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: January 8, 2013
    Assignee: SK Hynix Inc.
    Inventor: Hyeng Ouk Lee
  • Patent number: 8350617
    Abstract: Various embodiments of a semiconductor apparatus are disclosed. In one exemplary embodiment, the semiconductor apparatus may include an internal voltage generation unit configured to generate an internal voltage having a voltage level corresponding to a code value of a voltage control code, a voltage comparison unit configured to compare a voltage level of a target voltage with a voltage level of the internal voltage, and a voltage control code generation unit configured to adjust the code value of the voltage control code based on the comparison result of the voltage comparison unit.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: January 8, 2013
    Assignee: SK Hynix Inc.
    Inventors: Je Il Ryu, Junw Seop Jung
  • Patent number: 8350618
    Abstract: A voltage generation circuit includes: a first and second rectification circuits; and one or more amplification units connected between the first and second rectification circuits and configured to amplify an output of the first rectification circuit and provide the amplified output to the second rectification circuit. The second rectification circuit generates a reference voltage.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: January 8, 2013
    Assignee: SK Hynix Inc.
    Inventor: Jae Boum Park
  • Patent number: 8344752
    Abstract: A semiconductor integrated circuit includes an impedance control signal generation block configured to transmit first impedance control signals and second impedance control signals through same signal lines at predetermined time intervals, and input/output blocks configured to separately receive the first impedance control signals and the second impedance control signals at corresponding time intervals and perform a data input/output operation based on set impedance.
    Type: Grant
    Filed: December 31, 2010
    Date of Patent: January 1, 2013
    Assignee: SK Hynix Inc.
    Inventor: Seong Hwi Song
  • Patent number: 8345495
    Abstract: A test circuit of a nonvolatile semiconductor memory apparatus includes a first switching unit, a second switching unit, and a third switching unit. The first switching unit is configured to selectively interrupt application of a pumping voltage for a sense amplifier to a sense amplifier input node. The second switching unit is configured to selectively decouple the sense amplifier input node and a sub input/output node. The sub input/output node is coupled with a data storage region. The third switching unit is configured to selectively connect a voltage applying pad and the sense amplifier input node.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: January 1, 2013
    Assignee: SK Hynix Inc.
    Inventors: Jung Hyuk Yoon, Yoon Jae Shin
  • Patent number: 8344783
    Abstract: A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: January 1, 2013
    Assignee: SK Hynix Inc.
    Inventors: Jae Bum Ko, Jong Chern Lee, Sang Jin Byeon
  • Patent number: 8339879
    Abstract: A repair circuit of a semiconductor apparatus includes a transmission control unit configured to generate first through nth (n is an integer equal to or greater than 2) control signals in response to a repair information signal, and enable all mth through nth control signals when the repair information signal indicating an mth (m is an integer equal to or greater than 1 and equal to or less than n) TSV is inputted; transmission units configured to allocate transmission paths for first through nth signals to first through nth TSVs and a repair TSV in response to the first through nth control signals; and receiving units configured to receive the signals transmitted from the first through nth TSVs and the repair TSV in response to the first through nth control signals.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: December 25, 2012
    Assignee: SK Hynix Inc.
    Inventors: Min Seok Choi, Young Jun Ku
  • Patent number: 8339885
    Abstract: Various embodiments of a data transfer circuit of a semiconductor apparatus are disclosed. In one exemplary embodiment, the data transfer circuit may include a first data line, a second data line, a first transfer unit configured to amplify data on the first data line in response to a first control signal and transfer amplified data to the second data line, and a second transfer unit configured to electrically connect the first data line to the second data line in response to a second control signal.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: December 25, 2012
    Assignee: SK Hynix Inc.
    Inventor: Byeong Chan Choi
  • Patent number: 8339894
    Abstract: An address delay circuit of a semiconductor memory apparatus includes a control pulse generation unit configured to generate a control pulse following a time corresponding to a predetermined multiple of cycles of a clock after a read write pulse is inputted; and a delay unit configured to output internal addresses when the control pulse is inputted, wherein the internal addresses are input as external addresses.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: December 25, 2012
    Assignee: SK Hynix Inc.
    Inventors: Jae Bum Ko, Jong Chern Lee
  • Patent number: 8334830
    Abstract: Disclosed is a liquid crystal driving device, which is without a gate PCB, having improved uniformity of screen, and a driving method thereof. The liquid crystal driving device comprises: a sequence recognition means for recognizing sequence of a pertinent gate driver IC by a pulse width of a vertical start signal inputted in synchronization with a vertical synchronous signal, and generating a Carry signal and location data of the pertinent gate driver IC; and gate-off voltage generation means for receiving a first gate-off voltage and the location data of the pertinent gate driver IC, and outputting a second gate-off voltage which is generated by subtracting a voltage attenuation quantity corresponding to the location data of the gate driver IC from the first gate-off voltage.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: December 18, 2012
    Assignee: SK Hynix Inc.
    Inventors: Dong Hwan Lee, Tae Hyuk Kwon
  • Patent number: 8335124
    Abstract: In one embodiment, an external signal input circuit of a semiconductor memory may include: an input block configured to receive a plurality of external signals and to generate a plurality of internal signals; and a control block configured to output one or more internal signals of the plurality of internal signals that correspond to a rank configuration of the semiconductor memory and to block output of one or more internal signals of the plurality of internal signals that do not correspond to the rank configuration.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: December 18, 2012
    Assignee: SK Hynix Inc.
    Inventor: Jae Bum Ko
  • Patent number: 8331183
    Abstract: A memory apparatus includes a temperature detection block configured to detect temperature of an internal circuit and output a temperature detection signal, a current control block configured to receive the temperature detection signal and generate a pulse control signal, and a write driver configured to provide a program pulse having a compensated level and width to a memory cell in response to the pulse control signal.
    Type: Grant
    Filed: December 31, 2010
    Date of Patent: December 11, 2012
    Assignee: SK Hynix Inc.
    Inventors: Sung Yeon Lee, Hyun Joo Lee
  • Patent number: 8331171
    Abstract: A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data input/output line based on an input/output mode; and a second data output section configured to align and output either data transmitted through the first input/output line or the second data input/output line based on the input/output mode and an address signal.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: December 11, 2012
    Assignee: SK Hynix Inc.
    Inventors: Jae Il Kim, Jong Chern Lee
  • Patent number: 8330527
    Abstract: Various embodiments of a fuse circuit of a semiconductor apparatus are disclosed. In one exemplary embodiment, the fuse circuit may include a fuse whose electrical connection state can be changed by an electrical stress applied thereto and a plurality of self boosting units configured to perform self boosting operations under the control of a rupture enable signal. The self boosting units may also be configured to generate stress voltages and supply the generated stress voltages to the fuse. The fuse circuit may also include a precharge unit configured to supply a precharge voltage to the fuse in response to a precharge signal and a cross-coupled latching amplification unit configured to sense a change in a voltage level of the precharge voltage supplied to the fuse, with reference to a reference voltage, and output a fuse state signal.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: December 11, 2012
    Assignee: SK Hynix Inc.
    Inventor: Hong Gyeom Kim
  • Patent number: 8330512
    Abstract: A clock generation circuit of a semiconductor apparatus includes a first phase detection block configured to compare initial phases of a reference clock signal and an output clock signal in response to an operation start signal, and output an initial phase difference detection signal corresponding to a comparison result; a second phase detection block configured to compare phases of the reference clock signal and the output clock signal, and output a phase detection signal corresponding to a comparison result; a variable unit delay block determined in a control range of the delay amount thereof in response to the initial phase difference detection signal, and configured to delay the reference clock signal by a delay amount corresponding to a voltage level of a control voltage and output the output clock signal; and a delay control block configured to generate the control voltage which has the voltage level corresponding to the phase detection signal.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: December 11, 2012
    Assignee: SK Hynix Inc.
    Inventors: Ki Han Kim, Dong Suk Shin
  • Patent number: 8324958
    Abstract: In one embodiment, a redundancy circuit may include a comparison unit configured to record a first repair address through fuse cutting, compare a comparison address with the first repair address, and output a comparison result signal; a first fuse enable unit configured to output a first fuse enable signal for repairing the first repair address; a second fuse enable unit configured to output a second fuse enable signal for repairing a second repair address; a first determination unit configured to output a first repair determination signal in response to receipt of the first fuse enable signal and the comparison result signal; and a second determination unit configured to output a second repair determination signal in response to receipt of an inverted signal of a value of the comparison result signal corresponding to the certain bit, remaining bits, and the second fuse enable signal.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: December 4, 2012
    Assignee: SK Hynix Inc.
    Inventor: Ki Hoon Lee
  • Patent number: 8325558
    Abstract: A block decoder of a semiconductor memory device includes a control signal generation circuit configured to output a control signal in response to a first address mixing signal, a second address mixing signal, and an enable period signal and a block selection signal generation circuit configured to generate a block selection signal for selecting a memory block in response to the control signal.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: December 4, 2012
    Assignee: SK Hynix Inc.
    Inventor: Je Il Ryu
  • Patent number: 8325546
    Abstract: A semiconductor memory apparatus includes a memory device having a first plane and a second plane and a repair address latch unit configured to latch a plurality of repair addresses outputted from the memory device. The apparatus also includes an address comparison unit configured to compare the plurality of repair addresses stored in the repair address latch unit and a first plane address and a second plane address which are sequentially inputted. A repair processing unit is configured to selectively activate corresponding memory cell groups of the first plane and the second plane in conformity with the comparison result of the address comparison unit under the control of a first plane signal, a second plane signal and a start pulse signal.
    Type: Grant
    Filed: December 31, 2010
    Date of Patent: December 4, 2012
    Assignee: SK Hynix Inc.
    Inventor: Sang Kyu Lee
  • Patent number: 8320188
    Abstract: A semiconductor apparatus includes a control voltage transfer unit configured to transfer a control voltage transmitted through first transmission lines, to second transmission lines in response to a select signal transmitted through a select signal transmission line; a select signal driving unit configured to drive the select signal to the select signal transmission line; and a voltage boosting control unit configured to float the select signal transmission line when a voltage level of the select signal transmission line increase to or above a target level.
    Type: Grant
    Filed: December 31, 2010
    Date of Patent: November 27, 2012
    Assignee: SK Hynix Inc.
    Inventors: Myung Jin Park, Sang Kyu Lee
  • Patent number: 8319520
    Abstract: An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: November 27, 2012
    Assignee: SK Hynix Inc.
    Inventors: Yong Ju Kim, Hyung Soo Kim, Hae Rang Choi, Jae Min Jang