Abstract: A machine for blanking an integrated circuit chip from a segment of a film strip held in a fixture, forming its leads, and placing the chip on a multilayer substrate. The fixtures are stacked in a magazine which is mounted on the machine. A transfer mechanism transfers one fixture at a time from the magazine to a punch press where the IC chip is blanked from its film segment, and its leads are formed. The punch is retracted, and a multilayer substrate, which is mounted on an X-Y table, is positioned by the table under the punch so that the excised chip is directly above a chip pad and the chip leads are above the chip lead pads of a predetermined chip pad. The punch is lowered to position the chip on its chip pad. The substrate is coated with an adhesive flux to retain the chips and their leads in place. The punch is retracted and the X-Y table is moved to clear the punch press. A microcomputer controls the machine.

Abstract: In a large scale data processing system employing partitioning, paging and segmentation techniques with a descriptor enforced access to storage areas, a method and apparatus for testing address formulation is disclosed. All fundamental steps in address preparation are preserved whether a single step formulation is possible, as when the page table words are present in associative memory, or a multiple step process is required, as when the page table words must be retrieved from main memory.

Abstract: A fluid cooling system for electronic systems particularly adapted to cool large scale integrated circuit chips mounted on substrates. The system has one or more heat exchangers through which a liquid coolant is circulated. Each heat exchanger has a flexible wall and is mounted so that its flexible wall is in close proximity to a surface of the substrate to be cooled. A low thermal impedance contact is made through the flexible wall of the heat exchanger between the substrate to be cooled and the coolant flowing through the heat exchanger because of the pressure of the coolant in the heat exchanger. The heat exchangers are connected into the cooling system through flexible conduits so that a heat exchanger can readily be moved out of contact with a substrate without disrupting the flow of coolant through the cooling system.

Abstract: A multiple-generating register generates one of several possible multiples of a binary number which is input thereto depending upon the informational content of a 3-bit control signal. For each data stage there exists a data selector circuit, a master/slave circuit, and an output buffer circuit. The device can be configured as an inverting shift register for test and diagnostic purposes. The device is implemented in current mode logic, and a portion of the circuitry operates on differential level signals for increased operational speed and efficiency.

Abstract: A current mode 20-bit memory is organized as four words each containing five bits. The memory comprises a clock circuit a data-in circuit, comprising a plurality of data selectors and master latch registers, a data-out circuit comprising two independent sets of output buffers, two independent read select circuits, a write select circuit, a 4x5 matrix of memory cells, and non-functional testing circuit. In one mode data may be independently read from any two words at the same time that data is written into any one word. In another mode, all bits in a selected word may be synchronously reset. In a third mode the storage elements associated with one selected word may be configured as an inverting shift register for testing and diagnostic purposes. The device is implemented in current mode logic, and a portion of the circuitry operates on differential level signals for increased operational speed and efficiency.

Abstract: A reusable fixture for a segment of a film strip having a flexible beam lead frame mounted on the segment and an integrated circuit chip bonded to the inner portions of the leads of the lead frame. The fixture is made from an integral laminar layer of a suitable material. The improvements are in providing a plurality of pairs of projections with protuberances which overlie, to a slight degree, the attachment webs of a segment. The fixture is also provided with detachment openings to provide access to the attachment webs which detachment openings facilitate removal of a segment from the fixture.

Abstract: An apparatus for utilizing a logical compare instruction is disclosed. The apparatus develops a data field descriptor associated with and describing the attributes of each of the operands of the compare instruction. If the operands have different formats, when matching the contents of a first operand to the contents of a second operand, one operand is converted at execution time of the compare instruction to a format consistent with the other operand. The apparatus determines whether the contents of the first operand is greater than, less than, or equal to the second operand.

Abstract: A data field descriptor extends the flexibility of operand accesses by defining the attributes of a data field with regard to length, location and form of data representation at execution time. This delay of binding the operand accesses until execution time supports both data independence and security by permitting programs to be compiled without any restrictions imposed by the attributes of data fields. At execution time the necessary information is provided through a register so that the data field information may be correctly processed. With this feature a program is permitted to survive the change in formats of its input and output files without repeatedly undergoing the expensive operation of compilation. Also permitted is processing of files containing data field values which are not uniformly formatted throughout the file but which are self-defining through a data field descriptor.

Abstract: Apparatus for blanking an integrated circuit (I.C.) chip and the chip's thin flexible ductile leads from a segment of film and forming the leads of the chip in a single operation of a hollow punch having cutting and forming edges and a hollow die having cutting edges with a forming block having forming edges positioned within the die. The punch and die are mounted on a punch press. Alignment pins are provided which at the beginning of each blanking and forming operation engage reference sprocket holes of a film segment to which an I.C. chip is mounted to accurately position the chip and its leads with respect to the punch and die. A pressure pad is mounted in the punch and presses the leads against a portion of the forming block to isolate the bonds between the leads and the integrated circuit chip from forces applied to the leads during cutting and forming.

Abstract: A method of protecting active and passive electronic components on a portion of one surface of a multilayer substrate of a micropackage from deleterious constituents of the ambient atmosphere, primarily water vapor. A segment of a thin, flexible, substantially nonpermeable and nonadhering membrane, or sheet, has its perimeter secured to the substrate by a bead of sealant adhesive. The exposed surface of the segment has applied to it a thicker coating of a substantially nonpermeable sealant adhesive material which adheres to the membrane and the bead of sealant adhesive. A small opening is formed through the coating and the segment to provide communication with the area between the surface of the substrate on which the components are mounted and the inner surface of the segment. The substrate is placed in a chamber which is substantially evacuated to remove gases trapped under the segment.

Abstract: A programmable data envelope detector indicates the presence of phase encoded data being transmitted to or received from a data storage medium. The detector generates an output signal at a predetermined time after detecting the presence of data and continues to provide such output signal for a predetermined time after detecting the end of data. The detector comprises a data pulse detector, three-count up-down counter, two multicount four-bit up-down counters, a microprogrammable control store and decoder, a compare circuit, and a latch circuit. The time periods at which the latch circuit generates the output signal are different depending upon the nature of the data transfer operation, such time periods corresponding to different microinstructions in the control store.

Abstract: A sequencer for assembling into a transferee magazine predetermined numbers of fixtures from a predetermined plurality of transferor magazines, each of which transferor magazines is adapted to hold a plurality of fixtures. Each of the fixtures stacked in a transferor magazine holds an integrated circuit (IC) chip of the same type. The transferor magazines are removably mounted on transferor bases mounted on a support member. Positoning means are also mounted on the support member and a transferee magazine is removably mounted on a transferee base secured to the positioning means. A transfer mechanism is mounted on the positioning means to transfer a fixture from a transferor magazine to the transferee magazine when the transferee magazine is in fixture transfer position with respect to a transferor magazine.

Abstract: A control circuit for a switching regulator comprised of silicon controlled rectifiers and inductive reactors is disclosed. The control circuit provides for fault detection and voltage regulation while using these output as control signals for a frequency variable gating mechanism to trigger the switching regulator so as to provide its maximum output capability.

Abstract: The invention disclosed reduces unrecoverable read errors from a magnetic tape resulting from the apparent lack of a cyclic check character (CCC), sometimes referred to as a cyclic redundancy check character, or a longitudinal check character (LCC), sometimes referred to as a longitudinal redundancy check character. The detector provides a variable read window to synchronize receipt of the CCC and/or LCC with their associated data blocks even though the CCC and/or LCC was not written in the appropriate time frame called for by the write specification of the tape in question.

Abstract: A magazine into which a plurality of fixtures holding integrated circuit chips can be inserted serially by a machine and from which the fixtures can be removed serially by a machine. The fixtures are loaded through an opening in the bottom of the magazine and are removed from the magazine through the same opening. The magazine provides protection to the fixtures and chips held by the fixtures during storage and handling encountered in the typical manufacturing environment for electronic systems. The magazine facilitates automating the processes of accumulating fixtures holding integrated circuits of a given type and of assembling in one magazine the desired number of fixtures holding integrated circuit chips of the appropriate types preparatory to mounting the chips on a multilayer substrate.

Abstract: A uniphase charge transfer device comprises a plurality of electrode pairs disposed over a layer of gate oxide which overlies a semiconductor substrate. Within the substrate are a plurality of first conduction regions which are doped to a conductivity type opposite to that of the substrate. The first conduction regions underlie the separations between electrode pairs, and each one is electrically connected to one member of each electrode pair. A plurality of second conduction regions in the substrate are of the same conductivity type as the substrate but are of a substantially greater density of impurity atoms, and each of the second conduction regions underlies a portion of the other member of each electrode pair. A single clock line is connected to that member of each electrode pair which overlies the second conduction region. By alternatingly applying a predetermined voltage to the single clock line, charge packets representing information are moved unidirectionally through the device.

Abstract: A time-independent CCD charge amplifier comprises first and second CCD lines each having a plurality of electrode pairs disposed over a layer of silicon dioxide overlying a semiconductor substrate. Two clocks which are in a predetermined phase relationship with respect to one another are connected to alternate electrode pairs. The second CCD line further comprises a clocked-source charge injector, the input gate of which is electrically coupled to the signal source, which in a preferred embodiment comprises a surface potential tap in the first CCD line. According to a preferred embodiment, charge is non-destructively sampled from the first CCD line and is amplified by a predetermined factor in the second CCD line.

Abstract: The invention comprises circuitry for systematically multiplying two arbitrary field elements in a Galois field GF(2.sup.m). Each element is represented by an m-bit binary number. The multiplicand field element is passed serially through a plurality of m-1 modulo multipliers. The multiplicand and the product from each of the m-1 modulo multipliers are passed through networks which are gated by bits of the multiplier field element forming partial products. The partial products are summed to form the bit representations of the final product.

Abstract: A multiple-generating register generates one of several possible multiples of a binary member which is input thereto in response to a respective one of a plurality of multiple-generating commands. The multiple-generating register comprises a control circuit for generating the multiple-generating commands in response to a three-bit control signal and comprises further a plurality of selector latch logic circuits. Each selector latch logic circuit receives as a first input a respective bit of the input binary number and receives as a second input the next lowest order bit of the input binary number, except that the selector latch logic circuit which receives as a first input the lowest order bit of the input binary number receives as a second input a zero-valued binary bit. The plurality of selector latch logic circuits generate a binary number that is a multiple of the input binary number, which multiple is equal to the input binary number times .+-.1, .+-.

Abstract: Apparatus for directly decoding and correcting double-bit random errors per word and for detecting triple-bit errors per word is disclosed. Said apparatus comprises a syndrome calculator which operates upon codewords received from memory and generates syndromes. The syndromes are operated upon and translated by a mapping device which generates pointers identifying the bits which are in error. The pointers are then passed through decoding means to generate error words which are summed with the received word from memory to provide a corrected codeword. The syndrome calculator may further provide a parity check signal to determine if a three-bit error is present, in which case the decoding means are not enabled and a signal is generated indicating that a triple-bit error has been detected which is not correctable.