Patents Represented by Attorney, Agent or Law Firm Williams, Morgan & Amerson
  • Patent number: 8349744
    Abstract: Enhanced efficiency of a stress relaxation implantation process may be achieved by depositing a first layer of reduced thickness and relaxing the same at certain device regions, thereby obtaining an enhanced amount of substantially relaxed dielectric material in close proximity to the transistor under consideration, wherein a desired high amount of stressed dielectric material may be obtained above other transistors by performing a further deposition process. Hence, the negative effect of the highly stressed dielectric material for specific transistors, for instance in densely packed device regions, may be significantly reduced by depositing the highly stressed dielectric material in two steps with an intermediate relaxation implantation process.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: January 8, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kai Frohberg, Uwe Griebenow, Katrin Reiche, Heike Berthold
  • Patent number: 8349740
    Abstract: In sophisticated semiconductor devices, stress-inducing materials may be provided above the basic transistor devices without any etch control or etch stop materials, thereby enabling an efficient de-escalation of the surface topography, in particular above field regions including closely spaced polysilicon lines. Furthermore, an additional stress-inducing material may be provided on the basis of the superior surface topography, thereby providing a highly efficient strain-inducing mechanism in performance-driven transistor elements.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: January 8, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ralf Richter
  • Patent number: 8349694
    Abstract: When forming the strain-inducing semiconductor alloy in one type of transistor of a sophisticated semiconductor device, superior thickness uniformity of a dielectric cap material of the gate electrode structures may be achieved by forming encapsulating spacer elements on each gate electrode structure and providing an additional hard mask material. Consequently, in particular, in sophisticated replacement gate approaches, the dielectric cap material may be efficiently removed in a later manufacturing stage, thereby avoiding any irregularities upon replacing the semiconductor material by an electrode metal.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: January 8, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Markus Lenski, Andy Wei, Martin Gerhardt
  • Patent number: 8349695
    Abstract: In sophisticated manufacturing techniques, the work function and thus the threshold voltage of transistor elements may be adjusted in an early manufacturing stage by providing a work function adjusting species within the high-k dielectric material with substantially the same spatial distribution in the gate dielectric materials of different thickness. After the incorporation of the work function adjusting species, the final thickness of the gate dielectric materials may be adjusted by selectively forming an additional dielectric layer so that the further patterning of the gate electrode structures may be accomplished with a high degree of compatibility to conventional manufacturing techniques. Consequently, extremely complicated processes for re-adjusting the threshold voltages of transistors having a different thickness gate dielectric material may be avoided.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: January 8, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Thilo Scheiper, Andy Wei, Martin Trentzsch
  • Patent number: 8352688
    Abstract: A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional memory system configured to receive an early release indication for a specified word of a group of words in a read set of an active transaction. The early release indication comprises a request to remove the specified word from the read set. In response to the early release request, the processing core removes the group of words from the read set only after determining that no word in the group other than the specified word has been speculatively read during the active transaction.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: January 8, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jaewoong Chung, David S. Christie, Michael P. Hohmuth, Stephan Diestelhorst, Martin T. Pohlack, Luke Yen
  • Patent number: 8352686
    Abstract: An efficient and effective compiler data prefetching technique is disclosed in which memory accesses may be prefetched are represented in linear induction expressions. Furthermore, indirect memory accesses indexed by other memory accesses of linear induction expressions in scalar loops may be prefetched.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: January 8, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Dz-ching Ju
  • Patent number: 8343837
    Abstract: The work function of a high-k gate electrode structure may be adjusted in a late manufacturing stage on the basis of a lanthanum species in an N-channel transistor, thereby obtaining the desired high work function in combination with a typical conductive barrier material, such as titanium nitride. For this purpose, in some illustrative embodiments, the lanthanum species may be formed directly on the previously provided metal-containing electrode material, while an efficient barrier material may be provided in the P-channel transistor, thereby avoiding undue interaction of the lanthanum species in the P-channel transistor.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: January 1, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Richard Carter, Sven Beyer, Joachim Metzger, Robert Binder
  • Patent number: 8343826
    Abstract: When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage on the basis of a silicon/germanium semiconductor alloy for adjusting appropriate electronic conditions in the channel region, the efficiency of a strain-inducing embedded semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by initiating a crystal growth in the silicon material of the gate electrode structure after the gate patterning process. In this manner, the negative strain of the threshold voltage adjusting silicon/germanium alloy may be reduced or compensated for.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: January 1, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
  • Patent number: 8344474
    Abstract: In a sophisticated metallization system, self-aligned air gaps may be provided in a locally selective manner by using a radiation sensitive material for filling recesses or for forming therein the metal regions. Consequently, upon selectively exposing the radiation sensitive material, a selective removal of exposed or non-exposed portions may be accomplished, thereby resulting in a highly efficient overall manufacturing flow.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: January 1, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert Seidel, Thomas Werner
  • Patent number: 8338885
    Abstract: During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strain-inducing area within a sidewall spacer structure. Due to the corresponding void formation in the spacer structure, a high tensile strain component may be obtained, in the adjacent channel region.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: December 25, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jan Hoentschel, Thomas Feudel, Ralf Illgen
  • Patent number: 8338892
    Abstract: In MOS transistor elements, a strain-inducing semiconductor alloy may be embedded in the active region with a reduced offset from the channel region by applying a spacer structure of reduced width. In order to reduce the probability of creating semiconductor residues at the top area of the gate electrode structure, a certain degree of corner rounding of the semiconductor material may be introduced, which may be accomplished by ion implantation prior to epitaxially growing the strain-inducing semiconductor material. This concept may be advantageously combined with the provision of sophisticated high-k metal gate electrodes that are provided in an early manufacturing stage.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: December 25, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Roman Boschke, Maciej Wiatr, Peter Javorka
  • Patent number: 8338314
    Abstract: In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of the second stress-inducing dielectric material, while, in other cases, the etch stop material may be selectively formed after the patterning of the first stress-inducing dielectric material. Hence, the dual stress liner approach may be efficiently applied to semiconductor devices of the 45 nm technology and beyond.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: December 25, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ralf Richter, Heike Salz, Robert Seidel
  • Patent number: 8341316
    Abstract: A method and apparatus are provided for controlling a translation lookaside buffer in connection with the execution of an atomic instruction. The method comprises identifying load instructions within a plurality of instructions to be executed, and placing the identified load instructions in a queue prior to execution. An atomic instruction identified in the queue is prevented from executing until the atomic instruction is the oldest instruction in the queue. The apparatus comprises a queue and a translation lookaside buffer. The queue is adapted to: identify an atomic instruction within a plurality of instructions to be executed; prevent execution of the atomic instruction until it is the oldest instruction in the queue; and send a virtual address corresponding to the atomic instruction and an atomic load signal in response to determining that the atomic instruction is the oldest instruction in the queue.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: December 25, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David Kaplan, Christopher D. Bryant, Stephen P. Thompson
  • Patent number: 8338894
    Abstract: Deep drain and source regions of an N-channel transistor may be formed through corresponding cavities, which may be formed together with cavities of a P-channel transistor, wherein the lateral offsets of the cavities may be adjusted on the basis of an appropriate reverse spacer regime. Consequently, the dopant species in the N-channel transistor extends down to a specific depth, for instance down to the buried insulating layer of an SOI device, while at the same time providing an efficient strain-inducing mechanism for the P-channel transistor with a highly efficient overall manufacturing process flow.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: December 25, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Sven Beyer
  • Patent number: 8338306
    Abstract: In a replacement gate approach, the polysilicon material may be efficiently removed during a wet chemical etch process, while the semiconductor material in the resistive structures may be substantially preserved. For this purpose, a species such as xenon may be incorporated into the semiconductor material of the resistive structure, thereby imparting a significantly increased etch resistivity to the semiconductor material. The xenon may be incorporated at any appropriate manufacturing stage.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: December 25, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jens Heinrich, Ralf Richter, Katja Steffen, Johannes Groschopf, Frank Seliger, Andreas Ott, Manfred Heinz, Andy Wei
  • Patent number: 8337404
    Abstract: Methods, systems, and apparatus for detecting an epileptic event, for example, a seizure in a patient using a medical device. The determination is performed by providing an autonomic signal indicative of the patient's autonomic activity; providing a neurologic signal indicative of the patient's neurological activity; and detecting an epileptic event based upon the autonomic signal and the neurologic signal.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: December 25, 2012
    Assignee: Flint Hills Scientific, LLC
    Inventor: Ivan Osorio
  • Patent number: 8338274
    Abstract: In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of a strain-inducing semiconductor alloy. To this end, strain relaxation implantation processes may be performed at the drain side according to some illustrative embodiments, while, in other cases, the deposition of the strain-inducing alloy may be performed in an asymmetric manner with respect to the drain side and the source side of the transistor.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: December 25, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Vassilios Papageorgiou, Gunda Beernink, Jan Hoentschel
  • Patent number: 8338293
    Abstract: During the patterning of via openings in sophisticated metallization systems of semiconductor devices, the opening may extend through a conductive cap layer and an appropriate ion bombardment may be established to redistribute material of the underlying metal region to exposed sidewall portions of the conductive cap layer, thereby establishing a protective material. Consequently, in a subsequent wet chemical etch process, the probability for undue material removal of the conductive cap layer may be greatly reduced.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: December 25, 2012
    Assignee: Advanced Micro Devies, Inc.
    Inventors: Christin Bartsch, Daniel Fischer, Matthias Schaller
  • Patent number: 8338284
    Abstract: In sophisticated semiconductor devices, strain-inducing materials having a reduced dielectric strength or having certain conductivity, such as metal nitride and the like, may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors. For this purpose, a strain-inducing material may be efficiently encapsulated on the basis of a dielectric layer stack that may be patterned prior to forming the actual interlayer dielectric material in order to mask sidewall surface areas on the basis of spacer elements.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: December 25, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kai Frohberg, Hartmut Ruelke, Volker Jaschke, Joerg Hohage, Frank Seliger
  • Patent number: 8339166
    Abstract: An integrated circuit device includes first circuitry including first logic devices and a clock tree for distributing a clock signal to the first logic devices and second circuitry including second logic devices and a clock gater operable to receive the clock signal and distribute the clock signal to the second logic devices. The clock gater comprises a programmable delay circuit.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: December 25, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Deepesh John, Sundararajan Rangarajan