Patents Represented by Attorney, Agent or Law Firm Winstead Sechrest & Minick
  • Patent number: 7150864
    Abstract: The present invention concerns a method for growing carbon nanotubes using a catalyst system that preferentially promotes the growth of single- and double-wall carbon nanotubes, rather than larger multi-walled carbon nanotubes. Ropes of the carbon nanotubes are formed that comprise single-wall and/or double-wall carbon nanotubes.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: December 19, 2006
    Assignee: William Marsh Rice University
    Inventors: Richard E. Smalley, Jason H. Hafner, Daniel T. Colbert, Ken A. Smith
  • Patent number: 7149818
    Abstract: A method for communicating a Physical Layer (PHY) mean square error (MSE) to an upper layer device driver includes: receiving a frame by the PHY; computing a MSE for the frame by the PHY; sending the MSE and the frame to a Media Access Control (MAC); inserting the MSE into a frame status frame (FSF) associated with the frame by the MAC; and sending the frame and the FSF to the upper layer driver software. With access to the PHY MSE, the upper layer driver software can compute the average mean square error (AMSE) and determine if a change in the payload encoding (PE), or data transmission rate, should be negotiated. In this manner, the data transmission rate can be optimized while maintaining a low error rate.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: December 12, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Peter Chow, Kishore Karighattam, Robert Williams, Whu-ming William Young
  • Patent number: 7147060
    Abstract: A method and system are provided for installing an oriented conduit section in a well-bore having a substantially non-vertical axis. In one example, the system comprises: means for inserting a conduit a the well-bore, wherein the conduit comprises a section to be oriented, means for applying, in the well-bore, a rotating force to the section to be oriented, whereby an oriented section results, and means for fixing the conduit in the well-bore. An instrumented conduit section is also provided, for orientation in a well-bore having a substantially non-vertical axis. Further, a method is provided for using a tool in a well-bore, the method comprising: inserting a casing in the well-bore, orienting the casing in the well-bore, wherein an oriented casing is defined, inserting the tool in the oriented casing, and orienting the tool in the oriented casing.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: December 12, 2006
    Assignee: Schlumberger Technology Corporation
    Inventors: Klaus B. Huber, A. Glen Edwards, Luc Laverdière
  • Patent number: 7141411
    Abstract: The present invention relates to a simple, safe, and efficient process for the complete bio-decaffeination of caffeine-containing solutions using fungus Pseudomonas alcaligenes CFR 1708, a method of isolating pseudomonas alcaligenes CFR 1708 useful for the bio-decaffeination of caffeine-containing solutions, a Pseudomonas alcaligenes strain of accession number CFR 1708, and a decaffeinated solution obtained by aforementioned process.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: November 28, 2006
    Assignee: Council of Scientific and Industrial Research
    Inventors: Munna Singh Thakur, Renu Sarath Babu Vegesna, Naikankatte Ganesh Karanth, Mandyam Chakravarathy Varadaraj
  • Patent number: 7142015
    Abstract: A buffer, logic circuit, and data processing system employing fast turn-off drive circuitry for reducing leakage. Leakage current in logic circuitry is managed by coupling and decoupling the voltage potentials applied to large, high-leakage devices. Circuitry includes a low leakage logic path for holding logic states of an output after turning off high-leakage devices. A fast turn-off logic path in parallel with the low leakage logic path is used to assert each logic state in the forward direction from input to output. The large output device in each fast turn-off path is relieved of leakage stress by asserting logic states at driver inputs that cause the driver to turn OFF after the output logic state has been asserted.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: November 28, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jente Benedict Kuang, Hung Cai Ngo, Kevin John Nowka
  • Patent number: 7143267
    Abstract: A method and multithreaded processor for dynamically reallocating prefetch registers upon the processor switching modes of operation. An execution unit may be coupled to a prefetch engine where the execution unit may be configured to receive prefetch instructions regarding prefetching data. The prefetch engine may comprise a plurality of prefetch registers. The execution unit may further be configured to load the plurality of prefetch registers with information regarding prefetching data obtained from the prefetch instructions. In a single thread mode of operation, the plurality of prefetch registers are allocated to be accessed by either a first or a second thread. In a multithread mode of operation, the plurality of prefetch registers are allocated to be accessed among the first and second threads.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: November 28, 2006
    Assignee: International Business Machines Corporation
    Inventors: Eric J. Fluhr, Cathy May, Balaram Sinharoy
  • Patent number: 7140041
    Abstract: A method, system and computer program product for detecting the dissemination of malicious programs. The degree of randomness in the Internet Protocol (IP) destination addresses of received IP packets to be forwarded to an external network may be detected by performing a hash function on the IP destination addresses thereby generating one or more different hash values. If a high number of different hash values were generated for a small number of IP packets examined, then random IP destination addresses may be detected. By detecting random destination IP addresses, the dissemination of a malicious program, e.g., virus, worm program, may be detected.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: November 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Clark Debs Jeffries, Charles Steven Lingafelt, Norman Clark Strole
  • Patent number: 7140002
    Abstract: A mechanism for automatically generating code, in particular high level source code for remotely accessing functionality running in a remote process is provided. Given a specified set of functionality, which may be defined via an interface, for providing functionality to a local process, the mechanism generates, in source code form, software for remotely accessing the functionality by an application running in another process, that is, for accessing the functionality by an application running a second process. The code may be generated at build time but before the actual build of a software product implementing the functionality.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: November 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Brandon Brockway, Michael Richard Cooper
  • Patent number: 7139213
    Abstract: The invention describes and provides multiple data path memories and systems utilizing such memories. Enhanced data throughput and bandwidth, while substantially simultaneously providing improved bus utilization, are some of the benefits. In peer-to-peer connected systems, multiple bank/access block/sector/sub-array with random data throughput can also be realized. A memory including a plurality of independently accessible memory banks, a READ BUS for selectively reading to a selected on of the memory banks, and a WRITE BUS independent of the READ BUS for selectively writing to a selected one of the memory banks, is described.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: November 21, 2006
    Assignee: Silicon Aquarius, Inc.
    Inventor: G. R. Mohan Rao
  • Patent number: 7137141
    Abstract: A method and computer program product for bypassing the initial sign-on of an underlying operating system with single sign-on capability. In one embodiment, a method comprises the step of providing an application framework which logs on a user with a first level of access in the underlying operating system thereby bypassing the initial sign-on screen of the underlying operating system. The method further comprises entering a logon input, e.g., userID and password, on a generated application framework sign-on screen by the user. The method further comprises comparing the logon input with an application framework security database to determine the level of access. If the user is only entitled to the first level of access, then the user is restricted to a first level of access. If the user is entitled to another level of access, then a switch user program may be executed to switch the level of access to a second level of access, i.e., change in the assortment and/or number of applications.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: November 14, 2006
    Assignee: International Business Machines Corporation
    Inventor: Mark Gregory McClanahan
  • Patent number: 7137080
    Abstract: An integrated circuit design has circuit macros made up of device cells. The cells are characterized by determining the leakage current dependency on various process, environmental and voltage parameters. When circuit macros are designed their leakage power is calculated using this data and multi-dimensional models for power and temperature distribution. Circuit macros are identified as timing-critical and timing-noncritical macros. Statistical methods are used to determine the average leakage sensitivities for the specific circuit macros designed. The designer uses the sensitivity data to determine how to redesign selected circuit macros to reduce leakage power. Reducing leakage power in these selected circuits may be used to reduce overall IC power or the improved power margins may be used in timing-critical circuits to increase performance while keeping power dissipation unchanged.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: November 14, 2006
    Assignee: International Business Machines Corporation
    Inventors: Emrah Acar, Anirudh Devgan, Sani R. Nassif
  • Patent number: 7134153
    Abstract: A cradle conversion system having a cradle moveable between at least one sofa position and a bed position. The system comprised of a cradle having a first and second deck and a locking mechanism for selectively securing the decks in a set angular position to one another.
    Type: Grant
    Filed: September 14, 2004
    Date of Patent: November 14, 2006
    Assignee: Lifestyle Solutions, Inc.
    Inventor: Abedan Kanthasamy
  • Patent number: 7133423
    Abstract: A method and system for maintaining synchronization in a home network is disclosed. The home network includes a host ethernet media access controller and an HPNA chip, where control frame and data frame pairs are transferred between the host ethernet media access controller (MAC) and the HPNA chip. The method and system include sending a null frame from the host ethernet MAC to the HPNA chip prior to the data frame, and recognizing the null frame on the HPNA chip as an indication that a next received frame will be the data frame, thereby maintaining synchronization between the control frame and the data frame pairs.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: November 7, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Peter K. Chow, Harand Gaspar
  • Patent number: 7129754
    Abstract: An LSDL circuit replaces the normal clock control of the pre-charge device for the dynamic node with a control signal that is logic zero whenever the circuit is in an active mode and is a logic one when the circuit is in standby mode. The pre-charge device holds the dynamic node at a pre-charged logic one state independent of the clock. During the logic one evaluate time of the clock, the logic tree determines the asserted state of the dynamic node. During the evaluate time, the asserted state is latched by the static LSDL section. The dynamic node then re-charges to the pre-charge state. Since the pre-charge device is not de-gated during the evaluate time, the dynamic node cannot be inadvertently discharged by noise causing an error. Likewise, since the clock does not couple to the pre-charge device a load is removed from the clock tree lowering clock power.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: October 31, 2006
    Assignee: International Business Machines Corporation
    Inventors: Hung C. Ngo, Jayakumaran Sivagnaname, Kevin J. Nowka, Robert K. Montoye
  • Patent number: 7130916
    Abstract: A method and system for reducing memory accesses by inserting qualifiers in control blocks. In one embodiment, a system comprises a processor configured to process frames of data. The processor may comprise a plurality of buffers configured to store frames of data where each frame of data may be associated with a frame control block. Each frame control block associated with a frame of data may be associated with one or more buffer control blocks. Each control block, e.g., frame control block, buffer control block, may comprise one or more qualifier fields that comprise information unrelated to the current control block. Instead, qualifiers may comprise information related to an another control block. The last frame control block in a queue as well as the last buffer control block associated with a frame control block may comprise fields with no information thereby reducing memory accesses to access information in those fields.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: October 31, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jean Louis Calvignac, Marco C. Heddes, Joseph Franklin Logan, Fabrice Jean Verplanken
  • Patent number: 7129859
    Abstract: Circuitry used to de-skew data channels coupling parallel data signals over a communication link employs SOI circuitry that is subject to generating pulse distortion due to the history effect modifying threshold voltages. To substantially eliminate the pulse distortion, data signals are XOR with a repeating scramble data pattern that generates scrambled data with a minimum average ratio of logic ones to logic zeros logic zeros to logic ones. The scrambled data is sent over the communication link and de-skewed in the SOI circuitry with little or no pulse distortion. The scramble data pattern is again generated at the receiver side of the communication link after a delay time to synchronize the logic states of the scramble data pattern that generated the scrambled data with the scrambled data at the receiver side. The delayed scrambled data pattern is again XOR'ed with the scrambled data to recover the data signal.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: October 31, 2006
    Assignee: International Business Machines Corporation
    Inventors: Daniel M. Dreps, Robert J. Reese, Hector Saenz
  • Patent number: 7129860
    Abstract: A parallel decompression system and method that decompresses input compressed data in one or more decompression cycles, with a plurality of tokens typically being decompressed in each cycle in parallel. A parallel decompression engine may include an input for receiving compressed data, a history window, and a plurality of decoders for examining and decoding a plurality of tokens from the compressed data in parallel in a series of decompression cycles. Several devices are described that may include the parallel decompression engine, including intelligent devices, network devices, adapters and other network connection devices, consumer devices, set-top boxes, digital-to-analog and analog-to-digital converters, digital data recording, reading and storage devices, optical data recording, reading and storage devices, solid state storage devices, processors, bus bridges, memory modules, and cache controllers.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: October 31, 2006
    Assignee: Quickshift, Inc.
    Inventors: Manuel J. Alvarez, II, Peter Geiger, Thomas A. Dye
  • Patent number: 7125533
    Abstract: A method for functionalizing the wall of single-wall or multi-wall carbon nanotubes involves the use of acyl peroxides to generate carbon-centered free radicals. The method allows for the chemical attachment of a variety of functional groups to the wall or end cap of carbon nanotubes through covalent carbon bonds without destroying the wall or endcap structure of the nanotube. Carbon-centered radicals generated from acyl peroxides can have terminal functional groups that provide sites for further reaction with other compounds. Organic groups with terminal carboxylic acid functionality can be converted to an acyl chloride and further reacted with an amine to form an amide or with a diamine to form an amide with terminal amine. The reactive functional groups attached to the nanotubes provide improved solvent dispersibility and provide reaction sites for monomers for incorporation in polymer structures. The nanotubes can also be functionalized by generating free radicals from organic sulfoxides.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: October 24, 2006
    Assignee: William Marsh Rice University
    Inventors: Valery N. Khabashesku, Haiqing Peng, Mary Lou Margrave, legal representative, Wilbur Edward Billups, Yunming Ying, John L. Margrave, deceased
  • Patent number: 7127562
    Abstract: A method and system for ensuring orderly forward progress in granting snoop castout requests. Masters may include a tag (“request tag”) in their transfer requests to a bus macro. The request tag indicates the order of the request issued by the master. If the bus macro determines that the transfer request is snoopable, then the bus macro broadcasts a snoop request that includes the request tag. If a snoop controller determines that the address in the snoop request is a hit to a modified coherency granule in an associated cache, then the master associated with that snoop controller transmits a castout request to the bus macro that includes the request tag associated with the snoop request. The bus macro uses the request tag to determine whether the castout request is a response to the oldest in a series of pipelined snoop requests to be serviced.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: October 24, 2006
    Assignee: International Business Machines Corporation
    Inventors: James Norris Dieffenderfer, Bernard Charles Drerup, Jaya Prakash Ganasan, Richard Gerard Hofmann, Thomas Andrew Sartorius, Thomas Philip Speier, Barry Joe Wolford
  • Patent number: 7125502
    Abstract: The present invention involves fibers of highly aligned single-wall carbon nanotubes and a process for making the same. The present invention provides a method for effectively dispersing single-wall carbon nanotubes. The process for dispersing the single-wall carbon nanotubes comprises mixing single-wall carbon nanotubes with 100% sulfuric acid or a superacid, heating and stirring under an inert, oxygen-free environment. The single-wall carbon nanotube/acid mixture is wet spun into a coagulant to form the single-wall carbon nanotube fibers. The fibers are recovered, washed and dried. The single-wall carbon nanotubes were highly aligned in the fibers, as determined by Raman spectroscopy analysis.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: October 24, 2006
    Assignee: William Marsh Rice University
    Inventors: Richard E. Smalley, Rajesh Kumar Saini, Ramesh Sivarajan, Robert H. Hauge, Virginia Angelica Davis, Matteo Pasquali, Lars Martin Ericson