Abstract: A system which includes a microprocessor (or microcontroller) and an auxiliary chip which monitors the system power supply voltage and performs related functions for the microprocessor. The microprocessor can access the auxilary chip to ascertain the power history. That is, the microprocessor can direct an interrupt to the auxilary chip, which will cause the auxiliary chip to respond with a signal which indicates to the microprocessor whether the power supply voltage is heading up or down. When the microprocessor is reset at power-up, the present invention permits the microprocessor to determine (by querying the auxiliary chip) whether the supply voltage is marginal, so that the microprocessor does not go into full operation until the supply voltage is high enough.

Abstract: A CMOS integrated circuit, in which the PMOS devices each include a buried channel region (26). The P+ source/drain regions (54) and (56) are separated from the channel region (26) by N-type lateral field isolating regions (58) and (60). Whenever a voltage negative enough to turn on the channel is applied, the isolating regions will be inverted by the electric fields from the comers of the gate. Thus, the value of the transistor's threshold voltage is not changed. However, these lateral field isolating regions provide an electric field modification which helps to minimize drain-induced barrier lowering, and thereby reduces the leakage current of the device in the off state. Preferably the lateral field isolating regions are formed by a doping which is maximal at the same depth (below the gate oxide) at which the threshold-voltage-adjust doping of the channel is maximal.The preferred CMOS process provides lateral field isolating regions on the PMOS devices, and also provides LDD regions on the NMOS devices.

Abstract: An integrate circuit companding amplifier for analog signals with digitally controlled gain. The expansion amplifier uses a square law with presentation of sign and the compression amplifier uses the inverse (square root law with preservation of sign). A digital potentiometer determines the gain, and peak detection plus feedback control of the potentiometer provides for automatic gain control. Three wire communication can program a fixed gain.

Abstract: A low-power timekeeping integrated circuit, using a double-buffered memory architecture: The user can freely read from user memory at any time, and an internal clock periodically updates a set of timekeeping registers. Transfer from the timekeeping registers to user memory (for update of the data) is performed as a block transfer, asynchronously and invisibly to the user. A special timing-window requirement is used to avoid access collision problems: each edge of the one-hertz oscillator signal is delayed slightly, and it is the delayed signal which actually clocks the update to the timekeeping registers. After a further small delay (long enough to allow for worst-case ripple-through delays in the timekeeping registers), a latched signal (NO.sub.-- RIPPLE, in the presently preferred embodiment) is driven active. The signal NO.sub.-- RIPPLE shows that any rippling has been completed and that access is safe. Thus, transfer will occur or not, but will never be cut short.

Abstract: A system architecture which provides efficient data communication, over a one-wire bus, with a portable data module which does not necessarily include any accurate time delay circuit whatsoever. The time delay circuit in the module can be extremely crude. An open-collector architecture is used, with electrical relations defined to absolutely minimize the drain on the portable module's battery. A protocol has been specified so that the module never sources current to the data line of the one-wire bus, but only sinks current. The protocol includes signals for read; write-zero; write-one; and reset. Each one-bit transaction is initiated by a falling edge of a voltage signal from a host. The time delay circuit in the module defines a delay, after which (in write mode) the module tests the data state of the data line. In read mode, after a falling edge of a voltage signal from the host the module does or does not turn on a pull-down transistor, depending on the value of the bit read.

Abstract: An integrated circuit temperature detector (thermometer) uses a temperature dependent oscillator to count up to a fixed number and thereby generate a time interval indicative of the temperature (a temperature-to-time converter). The time-to-number converter provides a numeric temperature output. Counting oscillations of a relatively temperature independent oscillator for the time interval may digitize the temperature measurement. Calibration and successive approximation iterations permit simple hardware to achieve good accuracy.

Abstract: An integrated circuit terminator for a SCSI bus with resistors made of laser-blowable fuses in an array and a reference voltage source made with a bandgap generator and a two stage amplifier including a dummy isolation stage for providing symmetrical mismatch currents.

Abstract: Interrupt circuitry for a processor comprises a plurality of interrupt inputs, an interrupt output, combinatorial logic with a plurality of combinatorial logic inputs connected to the plurality of interrupt inputs and with a combinatorial logic output connected to the interrupt output wherein an interrupt output signal at the interrupt output is a function of interrupt signals at the plurality of interrupt inputs; and an interrupt mode select connected to the combinatorial logic wherein an interrupt mode select signal from the interrupt mode select controls the function. The interrupt mode select signal from the interrupt mode select selects the function to be either AND or OR.

Abstract: Reset monitor for detection of power failure and external reset for devices such as microprocessors with the reset monitor providing a single settling time hold down of a reset signal. Preferred embodiments include bandgap reference with high current side compensating resistor, bond out options for analog parameter selection, glitch free state machine control of both detections, and external pushbutton debouncing both depression and release.

Abstract: A low-power integrated circuit clock/calendar, wherein separate data busses are used for the time data and the alarm data. Conditional logic is used to only compare seconds bits (unless a match occurs, in which case higher-order bits are then compared). Thus, charging and discharging of the data busses (which carrying the time data) occurs only when a data transition is occurring. A special clocked latch circuit is used to hold the potential of each line of the time data bus constant, except when the data on the bus is actually changing. These innovations help to provide extremely long battery lifetime, since charge is not consumed by unnecessarily charging and discharging busses. Preferably this bus architecture is combined with a low-power logic architecture.

Abstract: Preferred embodiments have an external RAM controlled by logic on an internal RAM with overlapping address space. Read requests from addresses in the overlapping portion are directed to internal RAM only by controlling the output enable signal of external RAM; contrarily, writes to addresses in the overlapping portion proceed in both internal and external RAM simultaneously.

Abstract: A system for protecting data in a CPU's internal register. To obtain write access to the protected register, a process must sequentially write first and second keywords to an access register, within a predetermined time window.

Abstract: A memory controller for supplying backup battery power when a main power supply voltage drops together with programmable plus power fail write protection. The controller includes supravoltage induced sleep mode operation, MOS switching between backup batteries during backup operation based on battery voltage levels and discharge circuitry for battery disposal.

Abstract: An integrated circuit which can be operated EITHER in a battery-backed mode OR in a battery-operated mode. This is accomplished without any necessity for bond options, mask alteration, laser writing, or fuse blowing. The integrated circuit of the presently preferred embodiment has one pin BAT for battery input, and another pin VCCI for connection to a system power supply. Two PMOS switches are provided to connect one of these two pins to an on-chip power supply VDD under appropriate conditions. In addition, the disclosed integrated circuit has a third pin which can alternatively be used for battery input. The logic which controls the PMOS switches ensures that they will not turn on if their respective power inputs VCCI or BAT are low.

Abstract: A system which includes not only a microprocessor (or microcontroller), but also an auxiliary chip which monitors the system power supply voltage and performs related functions for the microprocessor, and also provides a watchdog function to monitor the microprocessor's activity. The auxiliary chip uses only two pins for the three functions of:active-high-reset out,active-low-reset out, andpushbutton reset input.

Abstract: A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.

Abstract: A CPU (28) accesses remotely disposed RAM (12) through a common serial data link. The RAM is interfaced to the common data link under the control of an arbiter circuit (10). The arbiter includes a protocol shift register (31) for receiving control information, ID information, and address information for the RAM. The incoming ID information is compared with an ID template (37), and:If a match IS present:Read/Write access to the RAM is allowed, andRead/Write access to the ID template is allowed;If a match is NOT present:NO access to the RAM is allowed,Read-Only access to the ID template is allowed.

Abstract: A digital potentiometer, in which the three terminals of the potentiometer are all free-floating. The position of the wiper is selected by a control signal received on a serial port. A change is made in the effective position of the wiper until the reset-bar signal goes low. Thus, the value of the potentiometer can be directly changed to any desired value, without intermediate incrementing steps. Moreover, this control arrangement allows multiple such potentiometers to share the same serial control bus, in a "daisy chain" configuration. This has the advantage that all of the potentiometers on the serial control bus will change their values at the same time. (This is advantageous, for example, in systems where such potentiometers are used to set the gain characteristics of multiple op amps.

Abstract: A dynamic PLA timing circuit in a PLA ROM includes a PLA line and the address section only of another PLA line. The address section of the first PLA line is connected to the true address lines and the address section of the other PLA line is connected to the complementary address lines. Shorting bars connecting the two PLA lines are formed around each pair of true and complementary address lines such that a conductive path is formed through the address sections for any address into the ROM. The data section is connected to the gates of every data transistor. However, the drains of all but one of the data transistors are not connected to their associated data line. The data line that is connected to the associated data transistor forms the output terminal of the timing circuit.

Abstract: A bidirectional voltage to current converter circuit with extended dynamic range includes a first and second operational amplifier in which the input voltage terminal is connected to the negative input of both operational amplifiers. The outputs of the operational amplifiers each directly drive the gates of two transistors which operate as a current mirror circuit. The current mirror transistors associated with the first operational amplifier are p-channel transistors with their sources connected to VDD, and the two transistors driven by the second operational amplifier are n-channel transistors with their sources connected to ground. The drains of the first p-channel transistor and the first n-channel transistor are coupled back to the positive inputs of the first and second operational amplifiers respectively; and also each drain is separately connected to one end of a resistor, the other ends of the two resistors are connected together and to a reference voltage.