Patents Represented by Law Firm Worsham, Forsythe, Sampels & Wooldridge
  • Patent number: 5267222
    Abstract: A low power timekeeping system utilizes a state machine to first read seconds stored in a RAM and update seconds and then determine if the minutes requires updating. If the minutes do not require updating then the sequencer stops operation until the next update cycle. Similarly, the minutes, hours, days of the week, date of the month, month, and year are updated only as needed in each update cycle thereby lowering the power requirement needed by the timekeeping system.
    Type: Grant
    Filed: June 18, 1991
    Date of Patent: November 30, 1993
    Assignee: Dallas Semiconductor Corp.
    Inventors: Clark R. Williams, William J. Podkowa
  • Patent number: 5260612
    Abstract: A transceiver (100) for TTL and RS232 communication with automatic sensing (130) of the type of input and adjustment of the output to correspond together with current stealing (131) from the input communication lines to provide extreme voltages for transmission. Hysteresis and surge suppression are built into the sensing.
    Type: Grant
    Filed: December 14, 1990
    Date of Patent: November 9, 1993
    Assignee: Dallas Semiconductor Corp.
    Inventors: Guenter H. Lehmann, William L. Payne, II
  • Patent number: 5258721
    Abstract: A telephone network interface integrated circuit with digitally based loop current detection and digitally based ring signal detection. The ring signal detection includes discrimination with a cutoff frequency of about 13 Hz to distinguish ring signals from dialing signals. The discrimination includes filtration followed by triggering an oscillator for one time period and checking whether the number of oscillations exceeds a threshold.
    Type: Grant
    Filed: August 27, 1990
    Date of Patent: November 2, 1993
    Assignee: Dallas Semiconductor Corp.
    Inventor: Gary V. Zanders
  • Patent number: 5249298
    Abstract: A power-switching device (such as a gate-controlled TRIAC) is used to connect and disconnect a computer system's power supply unit from the power-line connection. This power-switching device is controlled by a battery-powered circuit. The battery-powered circuit monitors a contact pad, and powers up the system when the user touches the contact. Thus, when the system is powered down, all parts of the system are disconnected from AC power.
    Type: Grant
    Filed: December 28, 1992
    Date of Patent: September 28, 1993
    Assignee: Dallas Semiconductor Corporation
    Inventors: Michael L. Bolan, Wendell L. Little
  • Patent number: 5243535
    Abstract: An integrated circuit containing two digital potentiometers with each potentiometer including a passive resistor string with tap points. Tap point selection is programmed through a three-wire serial port. An output multiplexing the selected tap points permits tying the two potentiometers in series to form a single potentiometer of twice the size.
    Type: Grant
    Filed: March 30, 1990
    Date of Patent: September 7, 1993
    Assignee: Dallas Semiconductor Corp.
    Inventors: Michael L. Bolan, Robert D. Lee, Gary V. Zanders
  • Patent number: 5237699
    Abstract: A battery-backed microprocessor which enters a known state on power-down. This is achieved, even if the microprocessor does not permit a single-cycle reset, by providing clock intercept circuitry on chip. When system power failure is detected, the clock intercept circuitry disconnects the external clock, activates a reset command, and then generates several clock cycles using an internal clock generator after the reset command. As many clock cycles are generated as is needed, with the particular architecture being used, to reach a predetermined state.
    Type: Grant
    Filed: May 8, 1992
    Date of Patent: August 17, 1993
    Assignee: Dallas Semiconductor Corp.
    Inventors: Wendell L. Little, Stephen N. Grider
  • Patent number: 5235548
    Abstract: A low-power SRAM with redundant rows in each of the subarrays. Conventional redundancy logic permits defective rows to be electrically replaced by redundant rows. In addition, power supply disconnect logic permits the V.sub.DD supply voltage line for the bad row to be disconnected.
    Type: Grant
    Filed: July 12, 1990
    Date of Patent: August 10, 1993
    Assignee: Dallas Semiconductor Corp.
    Inventor: Hal Kurkowski
  • Patent number: 5226137
    Abstract: An electronic key integrated circuit which includes three independently addressable partitions of secure memory. Each of these three partitions can function as a separate "subkey." Each of the subkeys is independently password-protected.In addition to the secure subkey memory partitions, the integrated circuit also contains a read/write "scratchpad" memory, which is the same size as each of the subkeys. After data has been written into the scratchpad (and verified if desired), it can be copied, as a block, onto one of the subkey partitions. However, to perform such a block move the password of the target subkey must also be specified.
    Type: Grant
    Filed: November 19, 1990
    Date of Patent: July 6, 1993
    Assignee: Dallas Semiconductor Corp.
    Inventors: Michael L. Bolan, Robert D. Lee
  • Patent number: 5223748
    Abstract: Battery monitor (100) with a transient pull down (172) for backup batteries which is active during power up and prevents the feedthrough charging of low or dead batteries causing a spurious power fail indication.
    Type: Grant
    Filed: December 11, 1990
    Date of Patent: June 29, 1993
    Assignee: Dallas Semiconductor Corp.
    Inventors: Eric W. Mumper, Donald R. Dias, Hal Kurkowski
  • Patent number: 5218225
    Abstract: A class of layout patterns for variable resistors and integrated circuits where the resistance is varied by varying a wiping point on a resistor line; contact is not made into the resistor line itself, but instead all contacts are made only to tabs which extend out from the resistor line. Preferred embodiments use a meander resistor line made of polysilicon within a silicon integrated circuit. Simple processing mask modifications can be used to change the geometry of the meander line to vary the resistance. The wiping point is digitally selected.
    Type: Grant
    Filed: March 30, 1990
    Date of Patent: June 8, 1993
    Assignee: Dallas Semiconductor Corp.
    Inventor: Gary V. Zanders
  • Patent number: 5218707
    Abstract: An integrated circuit wherein remapping logic permits the output-driver characteristics of a given pin to changed in software, by changing the data stored in a nonvolatile control bit.
    Type: Grant
    Filed: October 28, 1988
    Date of Patent: June 8, 1993
    Assignee: Dallas Semiconductor Corp.
    Inventors: Wendell L. Little, Francis A. Scherpenberg, Clark A. Williams, William J. Podkowa
  • Patent number: 5210846
    Abstract: A system architecture which provides efficient data communication, over a one-wire bus, with a portable data module which does not necessarily include any accurate time delay circuit whatsoever. The time delay circuit in the module can be extremely crude. An open-collector architecture is used, with electrical relations defined to absolutely minimize the drain on the portable module's battery. A protocol has been specified so that the module never sources current to a data line of the one-wire bus, but only sinks current. The protocol includes signals for read; write-zero; write-one; and reset. Each one-bit transaction is initiated by a falling edge of a voltage signal from the host. The time delay circuit in the module defines a delay, after which (in write mode) the module tests the data state of the data line. In read mode, after a falling edge of a voltage signal from the host the module does or does not turn on a pull-down transistor, depending on the value of the bit read.
    Type: Grant
    Filed: May 15, 1989
    Date of Patent: May 11, 1993
    Assignee: Dallas Semiconductor Corporation
    Inventor: Robert D. Lee
  • Patent number: 5206905
    Abstract: An electronic key which includes a pseudo-random number generator. If the correct password is received, the contents of a secure memory will be outputted by the electronic key. However, if an incorrect password is received, that password will be used as a seed value for the pseudo-random number generator, and the resulting value will be outputted.Thus, if a copier exercises the key through all possible passwords, the incorrect passwords, as well as the correct password, will result in the same output data every time it is tried.
    Type: Grant
    Filed: November 19, 1990
    Date of Patent: April 27, 1993
    Assignee: Dallas Semiconductor Corp.
    Inventors: Robert D. Lee, Stephen M. Curry, Scott J. Curry
  • Patent number: 5203000
    Abstract: A system which includes a microprocessor (or microcontroller) and an auxiliary chip which monitors the system power supply voltage and performs related functions for the microprocessor. In one mode of operation (for use with a low-power CMOS processor), the auxiliary chip sends an interrupt to the microprocessor when the power supply falls to a first level, and also resets the microprocessor when the supply voltage reaches a second preset level on the way up (i.e. while power is being restored). In a selectable second mode of operation (for use with NMOS processor), the auxiliary chip resets the processor when the power supply is on the way down.
    Type: Grant
    Filed: November 15, 1990
    Date of Patent: April 13, 1993
    Assignee: Dallas Semiconductor Corp.
    Inventors: Don Folkes, Wendell L. Little
  • Patent number: 5200751
    Abstract: A digital to analog converter, wherein a time/voltage array is programmable, to determine which of the possible reference voltages will be enabled by which of the control inputs. Anther set of programmable options, in an output connection matrix, determines which of the internal voltage lines will be connected to which output lines. After the output connection matrix, output selection logic is used to determined which class of output levels are to be used. The output selection logic also preferably includes polarity-reversal gates, so that the polarity of a bipolar output can be reversed.
    Type: Grant
    Filed: June 26, 1989
    Date of Patent: April 6, 1993
    Assignee: Dallas Semiconductor Corp.
    Inventor: Michael D. Smith
  • Patent number: 5199263
    Abstract: A coal-fired power plant with a wet scrubber wherein sulfite or bisulfite ions are converted to sulfate ions by forced aeration in the scrubber reaction tank. Air bubbles are introduced at only a few points in the tank, but an impeller is used which continually sweeps fine particulates off the tank bottom until they have reached a certain minimum size.
    Type: Grant
    Filed: August 12, 1991
    Date of Patent: April 6, 1993
    Assignee: Texas Utilities Electric Co.
    Inventors: Terence W. Green, Melanie K. Lange
  • Patent number: 5197142
    Abstract: Arbitration logic is provided to receive conflicts between a timekeeping system and a user system which share a common memory. The common memory is comprised of an array of dual memory cells, each of which has a timekeeping cell and a user cell and circuitry for transferring data from the timekeeping cell to the user cell or from the user cell to the timekeeping cell. User data is written into the user cells when it is available and immediately thereafter is transferred from the user cells to the timekeeping cells. Data from the timekeeping system is inhibited from being written into the timekeeping cells if, during the present update cycle of the timekeeping system, the user writes data into the common memory.
    Type: Grant
    Filed: January 22, 1991
    Date of Patent: March 23, 1993
    Assignee: Dallas Semiconductor Corp.
    Inventors: Clark R. Williams, William J. Podkowa
  • Patent number: 5194761
    Abstract: A waveform generating circuit, wherein a master clock signal is fed into a tapped string of adjustable delay lines, and the tapped delay outputs are used to control selection of scaled voltage fractions for output. The use of adjustable delay lines means that very high time-domain resolution can be achieved, simply by making a small adjustment to the value of a trimmable capacitor.
    Type: Grant
    Filed: May 11, 1992
    Date of Patent: March 16, 1993
    Assignee: Dallas Semiconductor Corp.
    Inventor: Michael D. Smith
  • Patent number: 5191554
    Abstract: A low-power low-voltage CMOS six-transistor static random access memory (SRAM), which can operate on a power supply voltage which is less than the sum of the NMOS and PMOS threshold voltages, does not include any analog or metastable sense amplifier stages. The selected cell is allowed to pull one of its bitline pair all the way down to ground. Thus, full logic levels appear on the bitline pair. Only one line of the bitline pair is connected to the following gate stage. Perferably bitline percharge transistors are connected to always pull up any unselected bitline pair.
    Type: Grant
    Filed: August 29, 1991
    Date of Patent: March 2, 1993
    Assignee: Dallas Semiconductor Corp.
    Inventor: Robert D. Lee
  • Patent number: RE34241
    Abstract: An embedded framing bit pattern in a serial bit stream is located by combining the last bit to arrive of the serial bit stream with a predetermined number of prior bits of the serial bit stream which are spaced apart by the pitch of the bits of the framing bit pattern, and this combination of the bits is tested to determine if the combination matches part of the framing bit pattern. If a match does not occur, then the bits which were combined together are changed to a bit pattern that will not result in a match when these bits (except for the eldest bit which is disregarded) is combined again with a new bit of the serial bit stream, no matter what the logic state of the new bit. In this manner all of the bits, as they arrive and are combined and tested, will eventually be changed except the bits which are part of the framing bit pattern.
    Type: Grant
    Filed: March 8, 1990
    Date of Patent: May 4, 1993
    Assignee: Dallas Semiconductor Corp.
    Inventor: Ching-Lin Jiang