Abstract: A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.

Abstract: A non-volatile memory array for an FPGA comprises a plurality of memory cells arranged in rows and columns and divided into a plurality of row segments. The source of each non-volatile memory transistor in each segment is coupled together to a common source line. A column segment line is associated with each segment of the array, and is coupled to the drains of each non-volatile memory transistor in the segment. A segment select transistor is coupled between each column segment line and its associated column line, and a high-voltage driver transistor is coupled to each column line.

Abstract: A split-gate memory cell, includes an n-channel split-gate non-volatile memory transistor having a source, a drain, a select gate over a thin oxide, and a control gate over a non-volatile gate material and separated from the select gate by a gap. A p-channel pull-up transistor has a drain coupled to the drain of the split-gate non-volatile memory transistor, a source coupled to a bit line, and a gate. A switch transistor has first and second source/drain diffusions, and a gate coupled to the drains of the split-gate non-volatile memory transistor and the p-channel pull-up transistor. An inverter has an input coupled to the second source/drain diffusion of the switch transistor, and an output. A p-channel level-restoring transistor has a source coupled to a supply potential, a drain coupled to the first source/drain diffusion of the switch transistor and a gate coupled to the output of the inverter.

Abstract: A computer program product in a computer-readable medium for use in a microcontroller-based control system in a programmable logic integrated circuit device is disclosed. The computer program product comprises first instructions for initializing the device, second instructions for reading programming data from a data source external to the programmable logic integrated circuit device, third instructions for transferring the programming data into control elements internal to the programmable logic integrated circuit device. Provision is made for fourth instructions for saving at least a part of the internal logic state of the user logic programmed into the programmable logic integrated circuit device into a non-volatile memory block and for fifth instructions for restoring at least a part of the internal logic state of the user logic programmed into the programmable logic integrated circuit device from a non-volatile memory block.

Abstract: A programmable system-on-a-chip integrated circuit device includes a programmable logic block. A digital input/output circuit block is coupled to the programmable logic block. A SRAM block is coupled to the programmable logic block. At least one non-volatile memory block is coupled to the programmable logic block. A JTAG port is coupled to the programmable logic block. An analog circuit block including an analog-to-digital converter may be coupled to the programmable logic block and an analog input/output circuit block may be coupled to the analog circuit block.

Abstract: An apparatus for generating a function activation signal to activate a function in an integrated circuit device comprises a power-on circuit receiving a power input and initializing and generating a test activation signal, a test circuit receiving the test activation signal and generating a test result signal, and a threshold decision circuit receiving the test result signal and generating the function activation signal. The test circuit models a function of the integrated circuit device and generates the test result signal when the power input has reached a sufficient voltage to perform the function of the integrated circuit device. The threshold decision circuit generates the function activation signal if the test result signal indicates the power input has reached a sufficient voltage to perform the function of the integrated circuit device.

Abstract: A method for providing a deglitching circuit for a radiation tolerant static random access memory (SRAM) comprising: providing a configuration memory having a plurality of configuration bits; coupling read and write circuitry to the configuration memory for configuring the plurality of configuration bits; coupling a radiation hard latch to a programmable element, the radiation hard latch controlling the programmable element; and providing an interface that couples at least one of the plurality of configuration bits to the radiation hard latch when the write circuitry writes to the at least one of the plurality of configuration bits.

Abstract: An integrated circuit includes a plurality of circuit groups, each circuit group containing a plurality of analog inputs, a buffer, a sample/hold circuit and a comparator. Each buffer has an input to which any of the analog inputs in its group may be programmably connected. The output of each buffer is coupled to the input of the sample/hold circuit in the group. The output of each sample/hold circuit is coupled to one input of a multiplexer. The output of the multiplexer is coupled to the input of an amplifier having programmable gain and programmable offset. The comparator in each group has inputs that may be programmably coupled to at least one analog input in the group or to a reference voltage source.

Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

Abstract: A fast, flexible carry scheme for use in clustered field programmable gate array architectures is described. Each cluster has a cluster carry input node, a cluster carry output node, a cluster carry output circuit having an output coupled to the cluster carry output node, a first input coupled to the cluster carry input node, and a second input and a plurality of logic modules each comprising a logic function generator circuit coupled to a carry circuit. The logic modules are coupled in a series carry arrangement between the cluster carry input node and the second input of the cluster carry output circuit such that the least significant bit of an arithmetic logic circuit can be programmably placed in any of the logic modules.

Abstract: A circuit and method for compensating sigma-delta modulators in A/D and D/A converters is disclosed. Circuits according to the invention use a low-resolution Sigma-Delta encoded version of the signal to inexpensively encode quadratic and cubic compensation terms. These circuits can encode quadratic and cubic compensation signals with acceptably low quantization noise without requiring the use of expensive multi-bit multipliers to compute the square or cube of the signal. The method includes providing a binary word Q or a binary word C (or both) representing the desired amount of quadratic or cubic compensation to apply. Because the encoded quadratic and cubic signals have only one or a few bits, they can be multiplied by Q and C without the use of expensive multi-bit multipliers and applied to the modulator input or output to provide a compensated result.

Abstract: An ESD protection circuit is disclosed for an n-channel MOS transistor formed in an inner p-well of a triple-well process and connected to an I/O pad that may experience both positive and negative voltages according to the present invention. A first switch connects the p-well containing the n-channel MOS transistor to ground if the voltage at the I/O pad is positive and a second switch connects the p-well containing the n-channel MOS transistor to the I/O pad if the voltage at the I/O pad is negative. A third switch connects the gate of the n-channel MOS transistor to the p-well if it is turned off and a fourth switch connects the gate of the n-channel MOS transistor to Vcc if it is turned on.

Abstract: An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between logical cells and accessibility to the hierarchical routing network. A second layer of routing network lines provides connectability between different first layers of routing network lines. Additional layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as the prior cell count in the array increases while the length of the routing lines and the number of routing lines also increases. Switching networks are used to provide connectability among same and different layers of routing network lines, each switching network composed primarily of program controlled passgates and, when needed, drivers.

Abstract: A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with voltage-measuring, current-measuring and control circuitry performs voltage measurement and control functions and can be used to control and monitor external power supplies connected to external loads.

Abstract: An ESD protection circuit includes a discharge transistor formed in a p-well and having a drain coupled to the I/O pad, and a source coupled to ground. A MOS capacitor has a gate coupled to the I/O pad. A first resistor is coupled between the source and drain of the MOS capacitor and ground. A pulldown transistor has a drain coupled to the source and drain of the MOS capacitor, a source coupled to ground, and a gate coupled to a power-supply voltage node. A p-well control transistor has a source coupled to ground, and a drain coupled to the p-well. A second resistor is coupled between the I/O pad and the drain of the p-well control transistor. A pump transistor has a gate coupled to the gate of the discharge transistor, a drain coupled to the I/O pad, and a source coupled to the p-well.

Abstract: An aggregation interconnect scheme for a programmable logic device provides low-skew routing of high fan-out signals by aggregating regional routing resources, which provide low-skew routing utilizing under-utilized global routing resources.

Abstract: A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment including a programming potential higher than the programming potential used in a previous programming segment, each programming segment followed by a zero-potential compare segment. The output of the flash memory cell is compared with the input data during the compare segment after each programming segment. The segmented programming pulse is terminated if the output of the flash memory cell matches the input data. The programming potential in each programming segment is increased during the programming segment. The programming potential in successive segments is either is increased or stepped up to the final value of the previous programming segment.

Abstract: An integrated circuit includes a plurality of inputs, a plurality of output pads, a programmable logic block, an analog circuit block, an analog-to-digital converter programmably coupleable to individual analog circuits in the analog circuit block, and an interconnect architecture programmably coupling selected ones of the plurality of inputs, the plurality of outputs, the programmable logic block, the analog circuit block, and the analog-to-digital converter. At least one of the inputs may be programmably configured as one of a digital input programmably coupleable to elements in the programmable logic block or as an analog input to an analog circuit in the analog circuit block.

Abstract: A flash-based programmable integrated circuit includes programmable circuitry, a flash memory array coupled to the programmable circuitry for configuring it, flash programming circuitry for programming the flash memory array, and an on-chip intelligence, such as a microcontroller or state machine, coupled to the programming circuitry to program the flash memory from off-chip data supplied via an I/O pad, or to refresh the data stored in the flash memory to prevent it from degrading.

Abstract: An integrated circuit includes at least one analog input. A sample/hold circuit is coupled to the at least one analog input. A reconfigurable delta-sigma ADC is coupled to the sample/hold circuit. A field programmable gate array is coupled to the reconfigurable delta-sigma ADC. A configurable on-chip clock source is coupled to the reconfigurable delta-sigma ADC providing control and reprogrammable oversampling ratio.