Abstract: Structures and operations of a resistive switching memory device are described herein. In one embodiment, a resistive switching memory device can include: a plurality of resistive memory cells, each configured to be programmed to a low resistance state by application of a first voltage in a forward bias direction, and erased to a high resistance state by application of a second voltage in a reverse bias direction; a plurality of common plates, each being connected to a subset of the resistive memory cells; a command detector configured to detect a write command to be executed as a first and second write operations; and a write controller configured to perform the first write operation on each resistive memory cell in a selected subset, and to perform the second write operation on at least one of the resistive memory cells in the selected subset based on the detected write command.

Abstract: A circuit can include at least one two terminal element programmable between at least two impedance states; a write section configured to place the element into different impedance states in a write mode; and a read section configured to generate an output value corresponding to the impedance state of at least one element in a read mode; wherein the at least one element draws substantially no current in a standard mode that is different from the write and read modes.

Abstract: A method of forming a conductive bridging memory cell can include forming an active electrode layer above a barrier layer formed on a lower conductive layer; forming at least one ion conductor layer over an active electrode layer; incorporating conductive ions into the ion conductor layer to create a switch memory layer that changes impedance in response to an electric field; and the active electrode layer is a source of conductive ions for the ion conductor, and the barrier layer substantially prevents a movement of conductive ions therethrough.

Abstract: A method can include determining at least one use characteristic for the memory cells comprising a solid electrolyte, the use characteristic corresponding to a number of times the memory cells have been programmed to at least one impedance level; and adjusting a read threshold level for the memory cells based on at least the use characteristic, the read threshold level determining data values stored in the memory cells in a read operation.

Abstract: In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.

Abstract: Structures and methods for controlling operation of a programmable impedance element are disclosed herein. In one embodiment, a method of programming/erasing the programmable impedance element can include: (i) receiving a program/erase command to be executed on the programmable impedance element; (ii) generating, in response to the program/erase command, a program/erase pulse for performing a program/erase operation on the programmable impedance element; (iii) generating a time delay from the program/erase pulse, where the time delay includes additional delay to allow for at least partial dissipation of one or more effects caused by the program/erase operation; and (iv) performing, after the time delay has elapsed, a verify operation to determine if the program/erase operation has successfully programmed/erased the programmable impedance element.

Abstract: A memory device can include at least two ports for transferring data to and from the memory device; and plurality of memory cells, each memory cell including at least one element programmable between different impedance states, and a plurality of access devices, each access device providing a current path between the element and a different one of the ports.

Abstract: A method can include determining a data value stored in a memory element of a memory cell array based on the length of time required to cause a property of the memory element to change. A memory device can include a plurality of elements programmable into at least two different states; and an electrical bias section that applies sense conditions to a selected element; and a sense section configured to distinguish between the two different states according to whether a change in property occurs in the selected element within a predetermined time under the sense conditions.

Abstract: In one embodiment, a method of operating a resistive switching device includes applying a signal comprising a pulse on a first terminal of a two terminal resistive switching device having the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period. The first time period is at least 0.1 times a total time period of the pulse.

Abstract: A memory device, comprising: read circuits coupled to a plurality of memory elements programmable between at least two different resistance states, the read circuits generating output values based on resistance states of selected memory elements in a read operation; and current limit circuits that limit a current flow through each memory element to less than a program threshold current; wherein the program threshold current corresponds to a current that flows through a memory element being programmed to cause its resistance to change to a resistance between that of two different resistance states.

Abstract: An integrated circuit may can include a memory section that stores data in programmable impedance elements arranged at cross points of select lines and sub bit lines, groups of sub bit lines each being connected to a different main bit line, the elements being formed above a substrate surface.

Abstract: A system can include a first memory section comprising a plurality of volatile memory cells accessible via a first data path having a first bit width; a second memory section comprising a plurality of programmable impedance memory cells, each having at least one solid electrolyte layer; and a second data path configured to transfer data between the first and second memory sections independent of the first data path, the second data path having a greater bit width than the first data path.

Abstract: A method can include electrically programming memory elements between first and second states; and reading data from the memory elements by applying electrical sense conditions; wherein a memory element in the first state takes a longer time to undergo a change in property under the sense conditions than a memory element in the second state.

Abstract: A resistive switching memory device can include a plurality of resistive memory cells, where each of the resistive memory cells includes: (i) a first diode having an anode coupled to a first word line and a cathode coupled to a common node; (ii) a second diode having an anode coupled to the common node and a cathode coupled to a second word line; and (iii) a resistive storage element having an anode coupled to a bit line and a cathode coupled to the common node, wherein the resistive memory cell is configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction, and to be erased to a high resistance state by application of an erase voltage in a reverse bias direction.

Abstract: A memory element can include a first electrode; a second electrode; and a memory material programmable between different resistance states, the memory material disposed between the first electrode and the second electrode and comprising a solid electrolyte with at least one modifier element formed therein; wherein the first electrode is an anode electrode that includes an anode element that is ion conductible in the solid electrolyte, the anode element being different than the modifier element.

Abstract: A method can include forming at least one memory layer over a first electrode, the memory layer having at least one element formed therein that oxidizes in the presence of an electric field to form conductive paths within the memory layer; and forming an inhibiting layer within the memory layer that increases an oxidation energy for the at least one element, as compared to the oxidation energy for the at least one element in the memory layer without the inhibiting layer.

Abstract: Structures and methods of operating a resistive switching memory device are disclosed herein. In one embodiment, a resistive switching memory device, can include resistive memory cells configured to be programmed to a low resistance state by application of a first voltage, and to be erased to a high resistance state by application of a second voltage; a detector configured to detect when at least one resistive switching memory cell is to be rendered inoperable; and a program/erase controller configured to render the at least one resistive switching memory cell inoperable by application of a third voltage during a program/erase operation, where the third voltage is greater in absolute value than the first or second voltage, and where the at least one resistive switching memory cell rendered inoperable remains in the low/high resistance state after subsequent erase/program operations.

Abstract: Structures and methods for encoding data to reduce write cycles in a semiconductor memory device are disclosed herein. In one embodiment, a method of writing data to a semiconductor memory device can include: (i) determining a number of significant bits for data to be written in the semiconductor memory device; (ii) determining a tag associated with the data to be written in the semiconductor memory device, where the tag is determined based on the determined number of significant bits; (iii) encoding the data when the tag has a first state, where the tag is configured to indicate data encoding that comprises using N bits of the encoded data to store M bits of the data, where M and N are both positive integers and N is greater than M; and (iv) writing the encoded data and the tag in the semiconductor memory device.

Abstract: Structures and methods for control of an operating window of a programmable impedance element are disclosed herein. In one embodiment, a semiconductor memory device can include: (i) a memory array having a programmable impedance element; (ii) a register configured to be programmed with data that represents an erase verify value, a program verify value, and a read trip point resistance value, for the memory array; (iii) a controller configured to determine a mode of operation for the memory array; (iv) a register access circuit configured to read the register to obtain data that corresponds to the mode of operation; and (v) a voltage generator configured to generate a reference voltage based on the register data, where the reference voltage is used to perform an operation on the programmable impedance element corresponding to the mode of operation.

Abstract: A memory cell includes a first resistive switching device having a first terminal and a second terminal, a switching device having a first terminal and a second terminal, and an access device having a first access terminal and a second access terminal. The first access terminal is coupled to the first terminal of the first resistive switching device and the first terminal of the switching device.