Abstract: A memory device can include a plurality of programmable impedance elements programmable between a low impedance state in response to a program voltage and a higher impedance state in response to an erase voltage having a different polarity than the program voltage; a programming circuit configured to apply the program and erase voltages to selected elements; and a pre-condition path configured to apply a pre-condition voltage only of the erase voltage polarity to fresh elements in a pre-condition operation; wherein fresh elements are elements that have not been subject to any programming voltages. The pre-condition electrical conditions can also include high voltage low current conditions that apply a greater magnitude voltage and smaller current than the first or second electrical conditions, or high voltage low current conditions that apply a greater magnitude voltage and greater current than the first or second electrical conditions.

Abstract: Structures and methods for controlling operation of a programmable impedance element are disclosed herein. In one embodiment, a method of programming/erasing the programmable impedance element can include: (i) receiving a program/erase command to be executed on the programmable impedance element; (ii) generating, in response to the program/erase command, a program/erase pulse for performing a program/erase operation on the programmable impedance element; (iii) generating a time delay from the program/erase pulse, where the time delay includes additional delay to allow for at least partial dissipation of one or more effects caused by the program/erase operation; and (iv) performing, after the time delay has elapsed, a verify operation to determine if the program/erase operation has successfully programmed/erased the programmable impedance element.

Abstract: Structures and methods for recovering data in a semiconductor memory device are disclosed herein. In one embodiment, a method of recovering data in a semiconductor memory device, can include: (i) pre-conditioning a first memory cell on the semiconductor memory device by using a formation voltage to program a first data state in the first memory cell; (ii) storing a second data state in a second memory cell on the semiconductor memory device by maintaining the second memory cell in a virgin state; (iii) mounting the semiconductor memory device on a printed-circuit board (PCB) by using a high temperature process that increases a resistance of the first memory cell; and (iv) performing a recovery of the first data state by reducing the resistance of the first memory cell.

Abstract: An integrated circuit (IC) device can include a plurality of memory cells with programmable impedance elements. A circuit can be configured to read a data value stored by an element of a memory cell by application of at least one read voltage pulse and at least one relaxation voltage pulse across the terminals of the element; wherein the read voltage pulse has a same polarity as a voltage used to program the element, the relaxation voltage pulse has a different polarity than the read voltage pulse, and neither the read or relaxation voltage pulses program the element to a particular impedance state.

Abstract: A method of operating a resistive switching device includes applying a program stress to a two terminal resistive memory unit. The program stress is applied at a program voltage configured to change a state of the memory unit from a first state to a second state. The method further includes applying a verification/stabilization stress to the two terminal resistive memory unit. The verification/stabilization stress is applied at a verification/stabilization voltage. An erase stress is applied to the two terminal resistive memory unit. The erase stress is applied at an erase voltage configured to change a state of the memory unit from the second state to the first state. The verification/stabilization voltage is between the program voltage and the erase voltage.

Abstract: A memory device can include a plurality of memory cells, each including a dynamic section configured to store data dynamically, and a programmable impedance section comprising at least one programmable element programmable between at least two different data states, the programmable impedance section configured to establish a data value stored by the dynamic section in response to a recall signal.

Abstract: Structures and methods for controlling operation of a programmable impedance element are disclosed herein. In one embodiment, a method of programming the programmable impedance element can include: (i) receiving a program command to be executed on the programmable impedance element; (ii) performing a program operation on the programmable impedance element in response to the program command; (iii) determining if the program operation successfully programmed the programmable impedance element; and (iv) performing an erase operation for programming the programmable impedance element in response to the program operation failing to successfully program the programmable impedance element.

Abstract: A memory device can include a plurality of memory elements programmable between different impedance states; and circuits configured to apply first electrical conditions to one group of memory elements and second electrical conditions, different from the first electrical conditions, to another group of memory elements to vary a speed of an access operation to the different groups of memory elements.

Abstract: A memory device can include a plurality of memory cells each comprising at least one programmable impedance memory element; a programming circuit coupled to the memory elements and configured to apply at least one time varying pulse to memory elements to place them into one of at least two different impedance states; and a programming voltage source coupled to the programming circuit configured to generate the at least one time varying pulse; wherein the time varying pulse decreases and increases in potential while having an overall increase in one voltage polarity.

Abstract: In accordance with an embodiment of the present invention, a method of operating a resistive switching device includes applying a signal including a pulse on a first access terminal of an access device having the first access terminal and a second access terminal. The second access terminal is coupled to a first terminal of a two terminal resistive switching device. The resistive switching device has the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period, a second ramp from the second voltage to a third voltage over a second time period, and a third ramp from the third voltage to a fourth voltage over a third time period. The second ramp and the third ramp have an opposite slope to the first ramp. The sum of the first time period and the second time period is less than the third time period.

Abstract: A memory device can include a plurality of memory elements formed over a substrate, including a plurality of first electrodes, each having a top surface and opposing side surfaces, a plurality of second electrodes formed on different vertical levels, each aligned with a corresponding first electrode in a lateral direction, and a memory material formed between each first electrode and an adjacent second electrode, the memory material being in contact with the opposing side surfaces of each first electrode and not in contact with the top surface of the first electrodes; wherein the memory material is electrically programmable between at least two different resistance states, and the lateral direction is parallel to a top surface of the substrate.

Abstract: According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material.

Abstract: An integrated circuit device can include a plurality of memory cells, each including at least one element programmable between different impedance states by application of a voltage or current; a plurality of bit line groups, each bit line group including multiple bit lines, each bit line being coupled to multiple memory cells; a plurality of current source circuits coupled to the bit line groups, each current source circuit configured to couple the bit lines of its respective group to at least a first bias node or a second bias node.

Abstract: Integrated circuit (IC) devices are disclosed that include programmable impedance elements (elements) as data storage element. In some embodiments, IC devices can include latch circuit with one or more elements that establish a function of an associated circuit. In other embodiments, IC devices can include elements arranged in a cross-point array connected to control terminals of access devices. In still other embodiments, a memory device can include a programmable address decoder. Corresponding methods are also disclosed.

Abstract: In accordance with an embodiment of the present invention, a resistive switching device includes an opening disposed within a first dielectric layer, a conductive barrier layer disposed on sidewalls of the opening, a fill material including an inert material filling the opening. A solid electrolyte layer is disposed over the opening. The solid electrolyte contacts the fill material but not the conductive barrier layer. A top electrode is disposed over the solid electrolyte.

Abstract: A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value for a memory element in response multiple sense results for the same memory element. In other embodiments, a memory device can include both standard and strong read operations, where strong read operations apply more energy to a selected memory element than a standard read operation.

Abstract: In one embodiment of the present invention, a memory cell includes a first resistive switching element having a first terminal and a second terminal, and a second resistive switching element having a first terminal and a second terminal. The memory further includes a three terminal transistor, which has a first terminal, a second terminal, and a third terminal. The first terminal of the three terminal transistor is coupled to the first terminal of the first resistive switching element. The second terminal of the three terminal transistor is coupled to the first terminal of the second resistive switching element. The third terminal of the three terminal transistor is coupled to a word line.

Abstract: A memory device can include a plurality of physical blocks that each include a number of memory elements programmable between at least two different impedance states, the memory elements being subject to degradation in performance; and bias circuits configured to applying healing electrical conditions to at least one spare physical block that does not contain valid data; wherein the healing electrical conditions are different from write operation electrical conditions, and reverse degradation of the memory elements of the at least one spare physical block.

Abstract: A programmable memory element can include an insulating layer formed over a bottom structure; an opening formed in the insulating layer; a sidewall structure formed next to side surfaces of the opening; a tapered structure formed within the opening adjacent to the sidewall structure; and a solid electrolyte forming at least a portion of a structure selected from: the bottom structure, the sidewall structure, and the tapered structure.

Abstract: In one embodiment, a resistive switching device includes a bottom electrode, a switching layer, a buffer layer, and a top electrode. The switching layer is disposed over the bottom electrode. The buffer layer is disposed over the switching layer and provides a buffer of ions of a memory metal. The buffer layer includes an alloy of the memory metal with an alloying element, which includes antimony, tin, bismuth, aluminum, germanium, silicon, or arsenic. The top electrode is disposed over the buffer layer and provides a source of the memory metal.