Patents Assigned to Advanced Semiconductor Engineering, Inc.
  • Patent number: 10950530
    Abstract: A semiconductor device package includes a first substrate, a second substrate, a first support element, a second support element and an electronic component. The first substrate has a first surface and a second surface opposite to the first surface. The first substrate has a conductive pad adjacent to the first surface of the first substrate. The second substrate is disposed over the first surface of the first substrate. The first support element is disposed between the first substrate and the second substrate. The first support element is disposed adjacent to an edge of the first surface of the first substrate. The second support element is disposed between the first substrate and the second substrate. The second support element is disposed far away from the edge of the first surface of the first substrate. The electronic component is disposed on the second surface of the first substrate.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: March 16, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Nan Lin, Jen-Chieh Kao
  • Patent number: 10950531
    Abstract: A semiconductor device package includes a first dielectric layer, a conductive pad and an electrical contact. The first dielectric layer has a first surface and a second surface opposite to the first surface. The conductive pad is disposed within the first dielectric layer. The conductive pad includes a first conductive layer and a barrier. The first conductive layer is adjacent to the second surface of the first dielectric layer. The first conductive layer has a first surface facing the first surface of the first dielectric layer and a second surface opposite to the first surface. The second surface of the first conductive layer is exposed from the first dielectric layer. The barrier layer is disposed on the first surface of the first conductive layer. The electrical contact is disposed on the second surface of the first conductive layer of the conductive pad.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 16, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Shun Chang, Teck-Chong Lee
  • Publication number: 20210074664
    Abstract: A semiconductor package structure includes a semiconductor device with an active surface, a conductive pillar on the conductive pad, an adhesion strengthening layer, and an encapsulant in contact with the adhesion strengthening layer. The conductive pillar has a side surface and a top surface. The adhesion strengthening layer is conformally disposed on the side surface of the conductive pillar and the active surface of the semiconductor device.
    Type: Application
    Filed: September 9, 2019
    Publication date: March 11, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Pin TSAI, Ming-Chi LIU, Yu-Ting LU, Kai-Chiang HSU, Che-Ting LIU
  • Publication number: 20210074676
    Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 11, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tang-Yuan CHEN, Meng-Kai SHIH, Teck-Chong LEE, Shin-Luh TARNG, Chih-Pin HUNG
  • Publication number: 20210076510
    Abstract: A semiconductor device package includes a display device, an encapsulation layer disposed in direct contact with the display device, and a reinforced structure surrounded by the encapsulation layer. The reinforced structure is spaced apart from a surface of the display device. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 11, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Hung CHEN, Yung I. YEH, Chang-Lin YEH, Sheng-Yu CHEN
  • Publication number: 20210074669
    Abstract: A semiconductor device package includes a connection structure having a first portion and a second portion extending from the first portion, the second portion having a width less than the first portion; and a dielectric layer surrounding the connection structure, wherein the dielectric layer and the second portion of the connection structure defines a space.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 11, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shun-Tsat TU, Pei-Jen LO, Fong Ren SIE, Cheng-En WENG, Min Lung HUANG
  • Patent number: 10943843
    Abstract: A semiconductor package structure includes a conductive trace layer, a semiconductor die over the conductive trace layer, a structure enhancement layer surrounding the semiconductor die, and an encapsulant covering the semiconductor die and the structure enhancement layer. The structure enhancement layer coincides with a mass center plane of the semiconductor package structure. The mass center plane is parallel to a top surface of the semiconductor die. A method for manufacturing the semiconductor package structure is also provided.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: March 9, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsiu-Chi Liu, Hsu-Nan Fang
  • Patent number: 10944363
    Abstract: The present disclosure relates to a power amplifier circuit. The power amplifier circuit includes a voltage-controlled current source and a current mirror. The voltage-controlled current source is configured to receive a first voltage and to generate a first current. The current mirror is connected to the voltage-controlled current source and to generate a second current in response to the first current. The second current continuously changes from 0 mA to about 120 mA as the first voltage continuously changes from 0 V to about 1 V.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: March 9, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Jaw-Ming Ding
  • Patent number: 10943800
    Abstract: An apparatus for packaging a semiconductor device is provided. The apparatus includes a first mold, a second mold and a support element. The first mold includes a plate. The second mold includes a carrier disposed corresponding to the plate. The carrier defines a hole penetrating the carrier. The support element is engaged with the hole for supporting an object to be molded.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: March 9, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Fan-Yu Min, Chao-Hung Weng, Liang-Chun Chen
  • Publication number: 20210066208
    Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a first dielectric layer, a first semiconductor element, a second dielectric layer, and at least one first conducive via. The first dielectric layer has a first top surface, a first bottom surface opposite to the first top surface, and a first side surface extending from the first top surface to the first bottom surface. The first semiconductor element is disposed adjacent to the first top surface of the first dielectric layer. The second dielectric layer has a second top surface, a second bottom surface opposite to the second top surface, and a second side surface extending from the second top surface to the second bottom surface, where the second dielectric layer covers a top surface of the first semiconductor element and the first side surface of the first dielectric layer.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20210066228
    Abstract: A package structure includes a base material, at least one electronic device, at least one encapsulant and a plurality of dummy pillars. The electronic device is electrically connected to the base material. The encapsulant covers the electronic device. The dummy pillars are embedded in the encapsulant. At least two of the dummy pillars have different heights.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20210066354
    Abstract: A semiconductor device package includes a main substrate, at least one thin film transistor (TFT) module, at least one first electronic component, at least one encapsulant and a plurality of light emitting devices. The main substrate has a first surface and a second surface opposite to the first surface. The thin film transistor (TFT) module is disposed adjacent to and electrically connected to the first surface of the main substrate. The first electronic component is disposed adjacent to and electrically connected to the first surface of the main substrate. The encapsulant covers the at least one thin film transistor (TFT) module and the at least one first electronic component. The light emitting devices are electrically connected to the at least one thin film transistor (TFT) module.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Hung CHEN, Yung I. YEH, Chang-Lin YEH, Sheng-Yu CHEN
  • Publication number: 20210066188
    Abstract: A package structure includes a base material, at least one electronic device, at least one dummy pillar and an encapsulant. The electronic device is electrically connected to the base material. The dummy pillar is disposed on the base material. The encapsulant covers the electronic device and a top end of the dummy pillar.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20210068267
    Abstract: A wiring structure includes a first dielectric layer, a second dielectric layer adjacent to the first dielectric layer, and a conductive region. The first dielectric layer defines a first opening, and the second dielectric layer defines a second opening. The conductive region includes a conductive via filling the first opening and the second opening. The conductive region further includes a first conductive trace embedded in the second dielectric layer and electrically connected with the conductive via. The conductive region includes a sidewall traversing through a thickness of the second dielectric layer with a substantial linear profile. A method of manufacturing a wiring structure is also disclosed.
    Type: Application
    Filed: August 27, 2019
    Publication date: March 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Min Lung HUANG
  • Publication number: 20210066218
    Abstract: A stacked structure includes a lower structure and an upper structure. The lower structure includes at least one lower dielectric layer and at least one lower metal layer in contact with the lower dielectric layer. The upper structure includes at least one upper dielectric layer and at least one upper metal layer in contact with the upper dielectric layer. The upper dielectric layer includes a first upper dielectric layer attached to the lower structure. The first upper dielectric layer includes a first portion and a second portion. A difference between a thickness of the first portion and a thickness of the second portion is greater than a gap between a highest point of a top surface of the first upper dielectric layer and lowest point of the top surface of the first upper dielectric layer.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Publication number: 20210066264
    Abstract: A semiconductor device package includes a first passive component having a first surface and a second passive component having a second surface facing the first surface of the first passive component. The first surface has a recessing portion and the second surface includes a protruding portion within the recessing portion of the first surface of the first passive component. A contour of the protruding portion and a contour of the recessing portion are substantially matched. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Application
    Filed: August 26, 2019
    Publication date: March 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Wen Chieh YANG
  • Publication number: 20210066156
    Abstract: A stacked structure includes a lower structure, an upper structure and a buffer layer. The lower structure includes at least one lower dielectric layer and at least one lower metal layer in contact with the lower dielectric layer. The upper structure includes at least one upper dielectric layer and at least one upper metal layer in contact with the upper dielectric layer. The buffer layer is interposed between the lower structure and the upper structure. A coefficient of thermal expansion (CTE) of the buffer layer is between a coefficient of thermal expansion (CTE) of the lower structure and a coefficient of thermal expansion (CTE) of the upper structure.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Patent number: 10939561
    Abstract: A wiring structure includes a first dielectric layer, a second dielectric layer adjacent to the first dielectric layer, and a conductive region. The first dielectric layer defines a first opening, and the second dielectric layer defines a second opening. The conductive region includes a conductive via filling the first opening and the second opening. The conductive region further includes a first conductive trace embedded in the second dielectric layer and electrically connected with the conductive via. The conductive region includes a sidewall traversing through a thickness of the second dielectric layer with a substantial linear profile. A method of manufacturing a wiring structure is also disclosed.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: March 2, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Min Lung Huang
  • Patent number: 10937761
    Abstract: A semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface; an electronic component disposed on the first surface of the substrate; a sensor disposed adjacent to the second surface of the substrate; an electrical contact disposed on the first surface of the substrate; and a package body exposing a portion of the electrical contact.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: March 2, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Ming Hung, Meng-Jen Wang, Tsung-Yueh Tsai, Jen-Kai Ou
  • Publication number: 20210057398
    Abstract: A semiconductor device package includes a first substrate, a dielectric layer, a thin film transistor (TFT) and an electronic component. The first substrate has a first surface and a second surface opposite to the first surface. The dielectric layer is disposed on the first surface of the first substrate. The dielectric layer has a first surface facing away from the first substrate and a second surface opposite to the first surface. The TFT layer is disposed on the dielectric layer. The electronic component is disposed on the second surface of the first substrate. A roughness of the first surface of the dielectric layer is less than a roughness of the first surface of the first substrate.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Hung CHEN, Sheng-Yu CHEN, Chang-Lin YEH, Yung-I YEH