Patents Assigned to Agere Systems Guardian Corp.
  • Patent number: 6549698
    Abstract: The limitation of N in an N×N Wavelength Grating Router (WGR) is determined to be because of the intrinsic diffraction characteristics of the grating that occurs when N approaches the diffraction order m at which the grating operates. The N in a N×N WGR device is maximized for input signal channels equally spaced either in frequency or in wavelength. For the wavelength case, N is increased by appropriate changes in the spacing of the output ports of the WGR and/or by slightly correcting the by channels wavelengths.
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: April 15, 2003
    Assignee: Agere Systems Guardian Corp.
    Inventors: Pietro Arturo Bernasconi, Christopher Richard Doerr, Corrado Pietro Dragone
  • Publication number: 20030062591
    Abstract: A wafer containing integrated circuits having fuses which are selectively blown to trim circuit perimeters. The fuses are located adjacent scribe lanes, and fuse pads are located in the scribe lanes. The integrated circuits are trimmed by selectively energizing the fuse pads to blow selective fuses. When the integrated circuits are severed from the wafer, the fuse pads are severed from the integrated circuits.
    Type: Application
    Filed: October 2, 2001
    Publication date: April 3, 2003
    Applicant: Agere Systems Guardian Corp.
    Inventors: William D. Jensen, David W. Kelly, Ronen Malka
  • Patent number: 6542539
    Abstract: Multiported register files for use in storing coefficients in adaptive FIR filters. incorporate computational ability, e.g., the ability to perform computation on coefficient values or derivatives thereof, or to control the operations performed thereon. For example, a multiported register file may incorporate an overflow/underflow detection and/or saturation unit. Also, the multiported register file may incorporate a special encoder to speed up the multiplication process, e.g., the so-called “Booth” encoder. Likewise, the multiported register file may incorporate a converter for changing the representation of the coefficients, e.g., a two's complement to sign-magnitude converter. All computation performed in the multiported register file is performed outside of the critical path of the filtering or of the coefficient updating. Using such improved multiported register files, adaptive FIR filters can be constructed which operate faster, and with lower power consumption.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: April 1, 2003
    Assignee: Agere Systems Guardian Corp.
    Inventors: Patrik Larsson, Christopher John Nicol
  • Patent number: 6541394
    Abstract: A method for making an oxide layer on a silicon substrate produces an oxide layer including graded portions with greatly reduced stress. The method includes growing a first oxide portion over a substrate by upwardly ramping the substrate to a first temperature lower than a SiO2 viscoelastic temperature. Thereafter a second oxide portion is grown between the first oxide portion and the silicon substrate by exposing the silicon substrate to an oxidizing ambient at a second temperature higher than the SiO2 viscoelastic temperature. The second oxide portion may have a thickness in a range of about 25 to 50% of a total thickness of the graded oxide layer.
    Type: Grant
    Filed: January 11, 2000
    Date of Patent: April 1, 2003
    Assignee: Agere Systems Guardian Corp.
    Inventors: Yuanning Chen, Sailesh Mansinh Merchant, Pradip Kumar Roy
  • Publication number: 20030058566
    Abstract: A magnetic data storage and retrieval system includes a magnetoresistive head, a resistor, a preamplifier circuit, a voltage measurement circuit, and a resistance calculation circuit. The preamplifier circuit is operably coupled to the magnetoresistive head and the resistor, and applies a first current to the magnetoresistive head and a second current to the resistor. The voltage measurement circuit measures a first voltage across the magnetoresistive head and a second voltage across the resistor. The resistance calculation circuit calculates a resistance of the magnetoresistive head based upon the first and second voltages.
    Type: Application
    Filed: September 26, 2001
    Publication date: March 27, 2003
    Applicant: Agere Systems Guardian Corp.
    Inventors: Boris Briskin, Jason A. Christianson, Ronen Malka
  • Publication number: 20030053528
    Abstract: A method and apparatus are disclosed for detecting a pilot signal in a wireless receiver using coherent combining/noncoherent detection techniques. Coherent combining/noncoherent detection techniques are used to detect the pilot signal whenever the receiver is already frequency locked, or otherwise known to have a small frequency offset. Conventional noncoherent combining/noncoherent detection techniques are utilized to initially acquire the timing of the forward channel. Once the receiver is frequency locked, coherent combining/noncoherent detection techniques may be used to continuously detect the pilot signals. After the receiver is frequency locked, the residue frequency error is small over several consecutive correlator outputs. The correlator outputs can thus be combined coherently (since the frequency error is known to be small), and the phase dependency is then eliminated by noncoherent detection.
    Type: Application
    Filed: November 7, 2002
    Publication date: March 20, 2003
    Applicant: Agere Systems Guardian Corp.
    Inventor: Xiao-an Wang
  • Patent number: 6522445
    Abstract: A support for a mirror which reflects a laser ray to a detector. The mirror is gimballed about two perpendicular axes. The mirror is supported solely by strain gauges. Rotation of the mirror about an axis causes one of the strain gauges to produce a signal indicative of the rotation. The signals are used as feedback signals to indicate position of the mirror, and thus position of the reflected ray.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: February 18, 2003
    Assignees: Lucent Technologies Inc., Agere Systems Guardian Corp.
    Inventor: Fred Kleytman
  • Patent number: 6519073
    Abstract: A method and apparatus for modulating an optical signal using a micromechanical modulator are disclosed. The modulator comprises a membrane, which includes a first and a second layer, a substrate layer, and a substrate, spaced from the membrane to form an air gap. The layers of the membrane are characterized in that there is a relationship between the refractive indices of the layers and the refractive index of the substrate. The membrane is suspended in a first position over the substrate by a flexible support arrangement. Bias is applied to the membrane and the substrate to create an electrostatic force to move the membrane towards the substrate to a second position. The reflectivity of the device to an optical signal changes as the membrane moves from the first position to the second position, thereby modulating the signal.
    Type: Grant
    Filed: January 10, 2000
    Date of Patent: February 11, 2003
    Assignees: Lucent Technologies Inc., Agere Systems Guardian Corp.
    Inventor: Keith Wayne Goossen
  • Patent number: 6518906
    Abstract: The performance of a single-bit cell in a DAC is improved by decoupling the voltage swing across the load resistors from the output of the current steering device. This can be achieved by providing for a single-bit cell having a first load resistor R1 and a second load resistor R2, a current steering circuit, and a decoupling circuit operably coupled between the current steering circuit and the resistors R1, R2. The current steering circuit steers at least part of a current I1 through a circuit path towards either the first resistor R1 or the second resistor R2. The decoupling circuit decouples voltage swings across the load resistors R1, R2 from the current steering circuit.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: February 11, 2003
    Assignee: Agere Systems Guardian Corp.
    Inventors: Christopher J Abel, Joseph Anidjar, Peicheng Ju
  • Publication number: 20030011400
    Abstract: Multiple level logic bus drivers and receivers communicate over a bus using a multiple-level logic protocol that transfers multiple bits on each signal wire of a bus in a given interval without increasing the bus width or power dissipation. In one embodiment, four logic levels are employed using CMOS transistor circuitry operating with low voltage (e.g., 1.2V or 1.3V) power supplies (Vdd) and P and N transistor threshold voltage levels of Vtp and Vtnon the order of 0.4-0.5V. Thus, the separation between the following four logic levels is approximately uniform: Vdd; Vdd−Vtp; Vss+Vtn; and Vss. The approximately equal voltage gaps between each quantization level provide uniform noise margins for all levels. A bus noise minimization scheme and a quick recovery scheme ensure the correct data transfer in the presence of injected noise. An initial over drive feature is disclosed for shorter transition times.
    Type: Application
    Filed: September 4, 2002
    Publication date: January 16, 2003
    Applicant: Agere Systems Guardian Corp.
    Inventors: Hyun Lee, Trevor Edward Little
  • Publication number: 20030014263
    Abstract: The present invention provides methods and systems for efficiently compressing information, such as speech data. By generating an excitation signal containing a number of zero and non-zero values and convolving the first signal with a known transfer function, a signal such as a codec residual signal can be compressed. While a convolution between any two signals can require a large number of multiply-and-accumulate operations, convolution between an excitation signal and impulse response can be made more efficient by multiplying only the non-zero values of the excitation signal with respective values of the impulse response.
    Type: Application
    Filed: April 20, 2001
    Publication date: January 16, 2003
    Applicant: AGERE SYSTEMS GUARDIAN CORP.
    Inventors: Jalaludeen Ca, Kaliamoorthy Ganesan, Vaidyanathan Karthigeyan
  • Patent number: 6507421
    Abstract: An optical crossconnect (OXC) fabric including an array of tiltable mirrors, a reflector and a plurality of optical fibers controls the position of the mirrors to optimize the transfer of a signal between an input optical fiber and an output optical fiber by monitoring the optical signal at an optical translation unit in each of the input optical fiber and the output optical fiber. The optical translation units are operable for regenerating the optical signals transmitted through the fibers.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: January 14, 2003
    Assignees: Lucent Technologies Inc., Agere Systems Guardian Corp.
    Inventors: David John Bishop, Randy Clinton Giles, David Thomas Neilson
  • Patent number: 6506673
    Abstract: The present invention provides a method that includes defining a dummy gate structure comprising a spin on glass on a semiconductor substrate, forming a dielectric layer over the dummy gate structure, removing the dummy gate structure to form a gate opening within the dielectric layer, and forming a gate material comprising a metal within the gate opening.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: January 14, 2003
    Assignee: Agere Systems Guardian Corp.
    Inventors: Yi Ma, Huili Shao, Joseph A. Taylor, Allen Yen
  • Publication number: 20030001241
    Abstract: The invention is a semiconductor device and method of fabricating the device. The device includes a semiconductor substrate with an active region, and a low dielectric constant insulating layer formed over the substrate. An additional insulating layer is formed over the low dielectric constant layer by a low temperature deposition, such as ion beam assistance deposition. A metal layer can then be formed over the additional layer using lift-off techniques. The metal layer can be patterned to form a bond pad which may be displaced from the area over the active region. Wire bonds can be made on the bond pad using ultrasonic energy.
    Type: Application
    Filed: May 28, 2002
    Publication date: January 2, 2003
    Applicant: Agere Systems Guardian Corp.
    Inventors: Utpal Kumar Chakrabarti, Bora M. Onat, Kevin Cyrus Robinson, Biswanath Roy, Ping Wu
  • Patent number: 6500729
    Abstract: A method for forming shallow trench isolation structures produces a shallow trench isolation structure having a substantially planar upper surface. The shallow trench isolation structure is formed from an originally formed shallow trench isolation structure which includes a deposited dielectric material within a trench and which exhibits dishing related problems in the form of a void formed within the trench, wherein the surface of the deposited dielectric material is recessed below the planar upper surface. The method provides for filling the void with a silicon film. The silicon film is then polished in its as-deposited or oxidized form, to produce a shallow trench isolation structure having a planar upper surface.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: December 31, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Sailesh Chittipeddi, Arun Kumar Nanda, Ankineedu Velaga
  • Publication number: 20020196573
    Abstract: A disk drive system including a write circuit for controlling current through a magnetic write head includes an H-switch circuit and a pulse-mode power supply circuit. The H-switch circuit controls direction of current through the magnetic write head. The pulse-mode power supply circuit is connected to the H-switch circuit for providing a higher voltage pulse at a beginning of a switching event of the H-switch circuit to accelerate a change in direction of current through the write head, followed by a lower voltage until a next switching event.
    Type: Application
    Filed: June 8, 2001
    Publication date: December 26, 2002
    Applicant: Agere Systems Guardian Corp.
    Inventors: Jong K. Kim, Elanguvan Nainar
  • Patent number: 6499087
    Abstract: A multiple agent system providing each of a plurality of agents, i.e., processors, access to a shared synchronous memory. A super agent is preferably that agent from among a plurality of agents which accesses a shared synchronous memory most frequently. The super agent has direct access to the shared synchronous memory, without negotiation and/or arbitration, while the non-super agents access the shared synchronous memory under the control of an arbiter-and-switch. Open windows are generated when the super agent is not, accessing the shared synchronous memory. The non-super agents can be allowed interim access to the shared synchronous memory even, before the super agent terminates ownership of the shared synchronous memory.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: December 24, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Jalil Fadavi-Ardekani, Bahram Kermani, Walter G. Soto, Richard J. Niescier, Fan You
  • Patent number: 6498080
    Abstract: A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: December 24, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Sailesh Chittipeddi, Taeho Kook, Avinoam Kornblit
  • Patent number: 6498931
    Abstract: Message retrieval methods and devices allow for the remote retrieval of caller identity delivery (“CID”) information or messages stored in telephones, telephone answering devices (“TAD”) and the like through the use of dual-tone, multi-frequency (“DTMF”) signals.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: December 24, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Barbara Mayak, John R. McElwee
  • Publication number: 20020190331
    Abstract: The present invention provides a semiconductor device and a method of manufacture therefor. The semiconductor device includes a semiconductor substrate having a gate formed there over. The semiconductor device further includes an isolation region having at least one source/drain region formed there over.
    Type: Application
    Filed: June 15, 2001
    Publication date: December 19, 2002
    Applicant: Agere Systems Guardian Corp.
    Inventor: Ian Wylie