Abstract: A preamplifier system is connected through an interconnect to a read head. The preamplifier system includes a voltage-sense preamplifier having at least one input connected through the interconnect to the read head and having at least one output, and also includes a current-sense preamplifier having at least one input connected through the interconnect to the read head and having at least one output. A summing circuit is connected to combine the outputs of the voltage-sense preamplifier and the current-sense preamplifier. For optimal performance, the preamplifier system is impedance matched to the interconnect. The preamplifier system achieves excellent response due to impedance matching with acceptably low noise levels, since the correlated noise associated with the current-sense preamplifier is canceled at the summing circuit.

Abstract: A preamplifier system is provided for connection through an interconnect to a read head. The interconnect has a characteristic impedance associated therewith. The preamplifier system includes an amplifier circuit having an input for connection to the interconnect. The amplifier circuit amplifies an input signal carried from the read head through the interconnect, yielding an amplified input output signal. A feedback resistance is connected between the amplified output signal and the input of the amplifier circuit. The feedback resistance has a value selected to provide an effective input impedance of the preamplifier system to match the characteristic impedance of the interconnect.

Abstract: A contactless, self-aligned local interconnect structure provides a continuous silicide film electrically coupling an upper silicon structure to a lower silicon structure. The upper silicon structure overlaps the lower silicon structure and is insulated from the lower silicon structure by an insulating layer formed between the structures. The continuous silicide film electrically couples the two structures by bridging the gap formed by the insulating layer in the overlap region. The associated process for forming the local interconnect structure includes forming a lateral edge of the upper silicon structure extending over the lower silicon structure, forming a blanket metal film, then heating the metal film such that the metal film reacts with the exposed silicon of the upper silicon structure and the lower silicon structure to form a continuous silicide film which bridges the gap formed by the insulating layer which is formed of a thickness chosen to be suitably low.

Abstract: We have found that a single crystal, single domain oxide layer of thickness less than 5 nm can be grown on a (100) oriented GaAs-based semiconductor substrate. Similar epitaxial oxide can be grown on GaN and GaN-based semiconductors. The oxide typically is a rare earth oxide of the Mn2 0 3 structure (e.g., Gd2O3). The oxide/semiconductor interface can be of high quality, with low interface state density, and the oxide layer can have low leakage current and high breakdown voltage. The low thickness and high dielectric constant of the oxide layer result in a MOS structure of high capacitance per unit area. Such a structure advantageously forms a GaAs-based MOS-FET.

Abstract: A waveguide for optical transmission having a mechanically active core material comprised of a silicon-rich silicon nitride in a mechanically active region. In the mechanically active region, the silicon-rich silicon nitride core can have no cladding (ie. an air cladding) or a cladding comprised of a silicon nitride over at least a portion thereof. The silicon-rich silicon nitride core is comprised of a silicon nitride compound having a ratio of silicon to nitrogen atoms greater than that of stoichiometric silicon nitride, Si3N4.

Abstract: An optical lens for use with an optical bench. The lens has a diffractive element which provides an angular offset to radiation incident on the lens. The offset substantially compensates for an undesirable focal point location caused by a variance between an integral component position on the bench and a desired position. The lens is particularly useful for an integral component position dictated by the bench crystal structure. In an illustrative embodiment an aspheric diffractive element deflects incident radiation by an amount in the range of about 8° to about 12°. Further disclosed is a method of compensation for variance between an integral component position on a bench and a desired position. Still further disclosed are an optical bench, a method for fabricating an optical bench and a semiconductor device.

Abstract: A shared correlator system and method for a code division, multiple access (CDMA) receiver employs pipeline processing and information tags for sharing vector generation and correlation operations between processing units. A signal input to the CDMA receiver is provided as, for example, In-phase channel (I) and quadrature-phase channel (Q) sample vectors IREC and QREC. Sample vectors IREC and QREC are applied to the shared correlator of the CDMA receiver. Processing units request correlation operations by the shared correlator in which matched filter pseudo-noise (PN) vectors are correlated with the I and Q sample vectors IREC and QREC. The shared correlator schedules correlation operations requested by processing units, generates matched-filter, PN vectors with associated identification tags for the correlation operations, and provides correlation results for the correlation operations.

Abstract: The present invention is an optical coupler comprising a plurality of optical fibers that have unclad (core-exposed) ends and tapered cladding regions extending to cladded ends. The core-exposed ends are arranged in a bundle, and the cladded ends can be arranged as needed. The optical coupler can efficiently couple between waveguides of different core areas and shapes. For example, it may be used to connect a multimode collection fiber having a core area of greater than 50 &mgr;m to a planar waveguide amplifier having waveguide strips with heights of 5 &mgr;m or less.

Abstract: It has been discovered that for semiconductor devices such as MOSFETs, there is significant capacitive coupling in the front-end structure, i.e., the structure from and including the device substrate up to the first metal interconnect level. The invention therefore provides a device comprising a silicon substrate, an isolation structure in the substrate (e.g., shallow trench isolation), an active device structure (e.g., a transistor structure), a dielectric layer over the active device structure, and a metal interconnect layer over the dielectric layer (metal-1 level). At least one of the dielectric components of the front-end structure comprise a material exhibiting a dielectric constant less than 3.5. This relatively low dielectric constant material reduces capacitive coupling in the front-end structure, thereby providing improved properties in the device.

Abstract: A differential voltage-controlled oscillator (VCO) employs a pair of accumulation-mode varactors driven with a differential control voltage to generate a differential oscillating waveform. The differential control voltage is formed from a pair of level-shifted input differential control voltage components. Level shifting of the input control voltages and driving the varactors with a differential control voltage allows for biasing of the varactors over a substantial range of capacitance variation. Such differential VCO may be employed within a phase-locked loop (PLL) circuit, with the pair of input control voltages being provided by the loop filter of the PLL circuit. The differential VCO comprises a differential control voltage to voltage converter (CV2VC) coupled to an LC-tank VCO. To improve common-mode noise rejection of the LC-VCO, the inductors of the LC-tank may be AC-coupled to the supply voltage, and the output differential oscillating waveform may be AC-coupled to the LC-tank through capacitors.

Abstract: Telephone line service type identification is provided to a telephone technician in the field by the placement of one or more tuned circuit(s) across the telephone line. In one embodiment, an inexpensive tuned circuit such as a ceramic resonator forms a telecom service resonator ID device which is placed across a telephone line, either at the central office or at the customer premises. Injection of a test current at a predetermined frequency, and a suitable amplitude of the same indicates to the technician aspects of telecom service to that particular telephone line (e.g., the existence of POTS, ISDN, and/or xDSL) and or use of the telephone line by a home network such as HPNA. In another embodiment, a telecom service transponder ID device is formed to provide line service identification to an interrogating line technician. The telecom service transponder ID device is activated when the test signal including an appropriate frequency is present to cause excitation in the telecom service transponder ID device.

Abstract: An integrated circuit package such as a BGA package for use with an integrated circuit chip. The integrated circuit package has substrate with a cavity that exposes a lower conductive level in the package so that connections between the integrated circuit chip and the lower conductive level may be formed to reduce the through holes formed in the substrate. As a result, additional signal line interconnections may be included in the substrate circuit package and/or the size of the integrated circuit chip may be decreased. Each of these may be implemented for enhanced electrical performance. The multiple wire bonding tiers in the substrate may also provide greater wire separation that eases wire bonding and subsequent encapsulation processes.

Abstract: A method for simulating a first processor (e.g., target processor) on a second processor (e.g., host processor) includes translating assembly language instructions associated with the first processor into ‘C’ language code. The ‘C’ language code is then compiled by a compiler program running on the second processor. The compiled code is then executed by the second processor to simulate the first processor. For example, the code may be checked to determine whether it is functionally correct and/or run-time statistics may be collected regarding the program associated with the first processor.

Abstract: A nanowire structure that may be used to fabricate small diameter and aligned nanowires, e.g., having a diameter of less than 50 nm and more preferably, less than 10 nm, is disclosed. The structure includes an alloy substrate having at least a first phase and a second phase, wherein the first phase is catalytic and the second phase is less catalytic (weakly or non-catalytic). A plurality of small diameter nanowires are grown from the first phase of the alloy substrate. Each one of the plurality of nanowires is substantially vertically aligned relative to the substrate and preferably, the average deviation from full vertical alignment is less than 25 degrees, and more preferably less than 15 degrees. The alloy substrate is fabricated with an alloy system of catalytic and non (or less) catalytic elements that are phase separated, e.g., by spinodal decomposition or nucleation-and-growth type transformation.

Abstract: An semiconductor device including logic circuitry, a plurality of pins, and an interface unit coupling the logic circuitry to the plurality of pins, wherein the interface unit permits any of the pins to be coupled to any portion of the logic circuitry. The semiconductor device provides a template by which many different types of semiconductor devices, with varied pin assignments, can be manufactured, without the need for changing production masks.

Abstract: A multi-chip module (“MCM”) and methods of operation and manufacture thereof. The MCM includes: (1) a substrate for supporting a plurality of separate integrated circuit (IC) chips thereon, (2) first and second separate IC chips mounted on the substrate, the first separate IC chip including first and second circuit portions coupled together by at least one signal conductor, and (3) interconnecting means that directly couples at least one signal conductor of the first separate IC chip to the second separate IC chip, the interconnecting means bypassing the second circuit portion of the first separate IC chip.

Abstract: A method and apparatus are disclosed for providing optical channel adding/dropping capability within a WDM filter-bypass device. The device comprises an optical filter, an optical switch, and means for receiving a control signal to configure the optical switch. When configured in a filter state, the switch routes the WDM signal through the filter to drop, add or drop and add one or more pre-selected WDM channels. When configured in a bypass state, the WDM signal bypasses the filter. A series of filter-bypass devices may be interconnected to increase the number of optical channels that can be dropped or added.

Abstract: A novel table look-up/indirect addressing system and method uses a dual fetch Harvard architecture to accomplish one full table look-up access per instruction cycle. The offset access fetch, the indirect data fetch and the table offset and base address addition are all performed during a single cycle. The system and method also accommodate data accesses using packed (half word) offsets.

Abstract: Methods and devices are provided for overcoming interference which occurs when one or more cordless devices seek to communicate over the same range of narrow band channels. Any one of a number of algorithms not based on channel clarity may be utilized to order groups of available channels which surround a cordless device. The device then selects a channel from within the ordered group of channels to assure clear communications between a cordless telephone handset and base. The algorithm may be randomly selected from among a number of algorithms or may be selected by other means.

Abstract: A method for testing a controller-data path RTL circuit using a BIST scheme without imposing any major design restrictions on the circuit. A state table is extracted from the controller netlist of the circuit using a state machine extraction program. The untested RTL elements/modules in the circuit are then selected, and the test control and data flow (TCDF) of the circuit are extracted from the controller/data path. Once the TCDF is extracted for the selected RTL elements, a symbolic testability analysis (STA) is performed to obtain test environments for as many untested data path elements as possible. The controller input sequence at the select signals of these test multiplexers needed for the particular test environment is noted and/or stored. A BIST controller is synthesized from the stored input sequences and the circuit is integrated with the BIST components using the thereby determined BIST architecture.