Abstract: A synchronous optical transmission system for interfacing SONET formatted channels to lower speed channels in either a SONET format or otherwise. The transmission system incorporates a fiber transmission system, terminal multiplexers and add/drop multiplexers that in turn incorporate a plurality of features, such as parallel scrambling circuitry, frame synchronization circuitry and the like.

Abstract: In a TDM telecommunications terminal, wherein multiple line cards are connected to a TDM bus, each line card location is provided with an identification code. A processor controlled circuit generates a programmable sequence of identification codes which are transmitted on a configuration bus in time slots synchronized with the time slots of the TDM bus. The configuration bus is connected to each of the line cards, which include a comparator logic circuit for comparing the identification of the line card location to the identification codes provided on the configuration bus. When a match is detected, the line card is enabled and is given access to the TDM bus. Through the programmable reassignment of time slots to line cards, concentration may be provided by the system, and a plurality of time slots may be assigned to a single line card to provide broad band service.

Abstract: A three-ported apparatus is adapted to interface a serial TDM bus, a local controller and a line unit bus in a telecommunications terminal. All data passing between the TDM bus and the line unit bus is temporarily stored and is accessible to the local controller, allowing the controller to either pass said data without modification or provide modifications thereto. Signaling contained within the data may be translated to a form usable by the line unit through the use of translation tables down-loaded from inventory storage on the line units. For each line unit, the local controller programmably controls time slot assignment, provisioning and inventory information access.

Abstract: A parallel frame synchronization circuit converts an incoming serial bit stream containing frame synchronization information into parallel data words on arbitrary boundaries of fixed bit length. Detectors forming part of the present invention determine from the parallel converted data the presence of synchronization information so as to align the incoming serial data into parallel data aligned on frame boundaries by manipulating parallel words. The present invention is particularly suited for fabrication in complimentary metal oxide silicon (CMOS) technology and in a preferred embodiment is used to synchronize incoming data comporting to the synchronous optical network (SONET) telecommunication standard.

Abstract: A transfer strobe delay stage selector insures accurate transfer of data from high speed circuitry to low speed circuitry through use of a delay stage module comprising a plurality of delay stages, and an associated multiplexor for selecting one of the delay stages so as to provide accurate reception of parallel data by the low speed circuitry from the high speed circuitry. The transfer strobe delay stage selector incorporates a synchronization channel identification module for detecting synchronization channel information in the frames of data transferred from the high speed circuitry to the low speed circuitry and also includes control circuitry for adjusting the selected delay stage until synchronization channel identification is detected.

Abstract: A serial transport frame format is described which transfers data between two locations. The serial transport frame format comprises a fixed number of channels per frame, each channel having a predetermined size. One channel per frame contains frame synchronization information and each channel which conveys data, contains a first portion for the transfer of data and a second portion which contains associated control information.

Abstract: A system that provides a signal in an assigned time slot of a multi-time slot repetitive frame, the assigned time slot being determined by input data that changes only on occasion, includes a flywheel circuit for reducing the chance that intermittent errors in the data input may cause the signal to be provided in an incorrect time slot. The flywheel circuit includes a time slot counter synchronized to provide a zero count during the assigned time slot and to initiate an output signal whenever the zero count occurs. The timing of a particular count of the counter is compared to the timing of the signal from the system during each frame, and if the timing does not correspond in a predetermined manner for a predetermined number of consecutive frames, the counter is re-synchronized to the timing of the signal from the system.

Abstract: A thermally controlled equipment cabinet for telephone systems has a gas-tight, sealed compartment for mounting sensitive active electronic components and has jacket 20 partially encompassing at least three sides of the sealed compartment. The sealed compartment utilizes either forced or natural convection to dissipate the heat generated by the components to the surrounding air. The heat is then dissipated to the ambient air through a highly heat-conductive corrugated roof and side panels. The jacket provides a cooling air passage around the sealed compartment and over the corrugated roof removing heat thereof. Nonsensitive passive components, mounted in the cooling air passage near the air inlet of the jacket, provide protrusions in the cooling air passage causing a slightly turbulent air flow in the passage thereby enhancing heat transfer. Storage batteries, such as used in telephone systems, are mounted within the cooling air passage near the air exhaust of the jacket.

Abstract: A variable length shift register is formed of a plurality of flip-flops arranged to form separate shift registers of different lengths. The shift registers are interconnected by multiplexers which connect either the input or the output of each shift register to the input of an adjacent shift register. Control signals are provided to the multiplexers to controllably select the length of the variable shift register by selectively inserting shift registers into the variable shift register and bypassing others.

Abstract: A system for aligning framing bits from independent digital transmission facilities with framing of a higher transmission rate facility includes a RAM memory. Received framing bits from the independent digital transmission facilities are stored at RAM locations in accordance with multiframe addresses of the framing bits relative to the multiframe format of the independent facility. Multiframe indicator bytes indicative of the framing of the higher transmission rate facility are used as addresses to read framing bits from RAM. The multiframe address of the independent digital transmission facilities is established by a counter for each independent facility, said counter being synchronized to the framing of the independent facility and incremented to provide addresses identical to the multiframe indicator bytes of the higher transmission rate facility.

Abstract: A parallel pseudo-random generator emulates a serial pseudo-random generator which in turn is defined by a polynomial of the type 1+x.sup.M + . . . +x.sup.P ; that is, wherein the serial outputs are generated such that the next serial output value is based upon an Exclusive OR combination of at least two preceding serial output values. The parallel pseudo-random generator comprises latches and Exclusive OR gates, the number of latches and Exclusive OR gates each being at least equal to the polynomial order of the serial pseudo-random generator defining polynomial. The outputs of the latches represent the outputs of the parallel pseudo-random generator and may be used to scramble data on parallel data lines. A method is disclosed for determining the interconnects between the latch outputs and the Exclusive OR gate inputs based upon the number of latches and the serial pseudo-random generator defining polynomial.

Abstract: A filtering algorithm for the SONET H4 byte is implemented with circuitry including an internal H4 counter which is incremented each frame and is locked to a received H4 byte once every 24 frames if a proper bit sequence is detected in a designated frame. If the designated bit sequence is not detected, the counter is not reset and continues to be incremented. If parity errors are detected, the counter is not reset and is allowed to free run to simulate the appropriate H4 byte input.

Abstract: A locking handle assembly used in combination with printed wiring boards and the like has camming portions which cooperate with a rod on the housing for the boards to act as a lever thereby positively seating and unseating its associated board within the housing. The handle assembly is provided with locking serrations. The serrations are positioned along radial curves so the handle is allowed to undertravel or overtravel, thereby compensating for tolerance buildup which could prevent proper seating of printed wiring assembly. An electrostatic discharge clip of the handle assembly engages the rod on the housing to ground the same and thereby prevent static electricity from the operator from producing an adverse effect on the electronic components.