Patents Assigned to Alpha and Omega Semiconductor (Cayman) LTD
  • Patent number: 10778101
    Abstract: A controller for a multi-phase switching regulator includes an error amplifier configured to generate an error signal indicative of the difference between a feedback voltage and a reference voltage; a loop calculator configured to generate control signals in response to the error signal to drive the power stages; and a dynamic phase management control circuit configured to generate a power efficiency value in response to the input current, the input voltage, the output current, and the output voltage. The dynamic phase management control circuit generates a phase selection signal indicating a first number of power stages to be activated in response to the first current signal and the power efficiency value. The phase selection signal is provided to the loop calculator to activate the first number of power stages.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: September 15, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventor: Richard Schmitz
  • Patent number: 10763125
    Abstract: A semiconductor device comprising a substrate layer, an epitaxial layer, a dielectric layer, a first aluminum layer, a first titanium interlayer and a second aluminum layer. The first titanium interlayer is disposed between the first aluminum layer and the second aluminum layer. A process for fabricating a semiconductor device comprising the steps of: preparing a semiconductor wafer; depositing a first aluminum layer onto the semiconductor wafer; depositing a first titanium interlayer onto the first aluminum layer; depositing a second aluminum layer onto the first titanium interlayer; applying an etching process so that a plurality of trenches are formed so as to expose a plurality of top surfaces of a dielectric layer; and applying a singulation process so as to form a plurality of separated semiconductor devices.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 1, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN), LTD.
    Inventors: Wei He, Chris Wiebe, Hongyong Xue
  • Patent number: 10763221
    Abstract: A high voltage (HV) converter implemented on a printed circuit board (PCB) includes a double diffused metal oxide semiconductor (DMOS) package comprising a lead frame and a main DMOS chip. The lead frame includes a gate section electrically connected to a gate electrode of the main DMOS chip, a source section electrically connected to a source electrode of the main DMOS chip and a drain section electrically connected to a drain electrode of the main DMOS chip. The PCB layout includes a large area source copper pad attached to and overlapping the source section of the DMOS package to facilitate cooling and a small area drain copper pad attached to and overlapping the drain section of the DMOS package to reduce electromagnetic interference (EMI) noise.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 1, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN), LTD.
    Inventors: Zhiqiang Niu, Kuang Ming Chang, Lin Chen, Ning Sun, QiHong Huang, Tzu-Hsin Lu
  • Patent number: 10756645
    Abstract: A power conversion system includes a bridge switch circuit. The bridge switch circuit includes a plurality of switch sub-circuits, each switch sub-circuit includes: a switch for controlling switching of the switch sub-circuit; and a control unit configured to perform the following control cycle: When the voltage between the switch and the cathode is less than the first voltage threshold and the switch sub-circuit is not charged, the control unit controls the switch to be turned on, and starts charging the switch sub-circuit. When the voltage between the switch and the cathode is greater than a second voltage threshold, the control unit controls the switch to be turned off. When the charging voltage of the control unit is greater than the third voltage threshold, the control unit stops charging the switch sub-circuit. The circuit structure is simple and the circuit energy loss of the bridge rectifier is reduced.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: August 25, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventor: Ming-Hsueh Chen
  • Patent number: 10720422
    Abstract: A bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating optimized collector-base junction realizing avalanche mode breakdown. In some embodiments, the bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating individually optimized collector-base and emitter-base junctions with the optimized junctions being spatially distributed. The optimized collector-base and emitter-base junctions both realize avalanche mode breakdown to improve the breakdown voltage of the transistor. Alternately, a unidirectional transient voltage suppressor is constructed as an NPN bipolar transistor with a PN junction diode connected in parallel in the reverse bias direction to the protected node and incorporating individually optimized collector-base junction of the bipolar transistor and p-n junction of the diode.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: July 21, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 10714580
    Abstract: A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device, comprising a substrate of a first conductivity type, a body region of a second conductivity type, a gate electrode formed in a gate trench extending in the body region and substrate, a lightly doped source region and a heavily doped source region formed in the body region, and a trench contact extending to the body region formed in a contact trench. A contact implant of the second conductivity type is formed surrounding a bottom portion of the contact trench and it also forms surrounding sidewall portions of the contact trench where it contacts with the lightly doped source region to form a PN diode.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: July 14, 2020
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventor: Sik Lui
  • Patent number: 10692851
    Abstract: A transient voltage suppressor (TVS) is constructed as an NPN bipolar transistor including individually optimized collector-base and emitter-base junctions both with avalanche mode breakdown. The TVS device is constructed using a base that includes a lightly doped base region bordered by a pair of more heavily doped base regions. The two more heavily doped base regions are used to form the collector-base junction and the emitter-base junction both as avalanche breakdown junctions. The lightly doped base region between the collector-base and emitter-base doping regions ensures low leakage current in the TVS device. In this manner, the TVS bipolar transistor of the present invention provides high surge protection with robust clamping while ensuring low leakage current.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: June 23, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Shekar Mallikarjunaswamy, Ning Shi
  • Publication number: 20200194347
    Abstract: A semiconductor package has a plurality of pillars or portions of a plurality of lead strips, a plurality of semiconductor devices, one or two molding encapsulations and a plurality of electrical interconnections. The semiconductor package excludes a wire. The semiconductor package excludes a clip. A method is applied to fabricate semiconductor packages. The method includes providing a removable carrier; forming a plurality of pillars or a plurality of lead strips; attaching a plurality of semiconductor devices; forming one or two molding encapsulations; forming a plurality of electrical interconnections and removing the removable carrier. The method may further include a singulation process.
    Type: Application
    Filed: December 18, 2018
    Publication date: June 18, 2020
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Yan Xun Xue, Xiaotian Zhang, Long-Ching Wang, Yueh-Se Ho, Zhiqiang Niu
  • Publication number: 20200194395
    Abstract: A semiconductor package has a plurality of pillars or portions of a plurality of lead strips, a plurality of semiconductor devices, one or two molding encapsulations and a plurality of electrical interconnections. The semiconductor package excludes a wire. The semiconductor package excludes a clip. A method is applied to fabricate semiconductor packages. The method includes providing a removable carrier; forming a plurality of pillars or a plurality of lead strips; attaching a plurality of semiconductor devices; forming one or two molding encapsulations; forming a plurality of electrical interconnections and removing the removable carrier. The method may further include a singulation process.
    Type: Application
    Filed: December 18, 2018
    Publication date: June 18, 2020
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Xiaotian Zhang, Yan Xun Xue, Long-Ching Wang, Yueh-Se Ho, Zhiqiang Niu
  • Patent number: 10686038
    Abstract: An RC-IGBT includes a semiconductor body incorporating a field stop zone where the base region and the field stop zone are both formed using an epitaxial process and the field stop zone has an enhanced doping profile to realize improved soft-switching performance for the semiconductor device. In alternate embodiments, RC-IGBT device, including the epitaxial layer field stop zone, are realized through a fabrication process that uses front side processing only to form the backside contact regions and the front side device region. The fabrication method forms an RC-IGBT device using front side processing to form the backside contact regions and then using wafer bonding process to flip the semiconductor structure onto a carrier wafer so that front side processing is used again to form the device region.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: June 16, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Hongyong Xue, Lei Zhang, Brian Schorr, Chris Wiebe, Wenjun Li
  • Patent number: 10665551
    Abstract: A trench-type metal-oxide-semiconductor field-effect transistor (MOSFET) device and a fabrication method are disclosed. A semiconductor substrate of a first conductivity type is provided. A plurality of first trenches arranged side by side in a first stripe layout extending along a first direction in a first preset area of the semiconductor substrate are formed. A plurality of second trenches arranged side by side in a second stripe layout extending along a second direction perpendicular to the first direction in a second preset area of the semiconductor substrate are formed. The plurality of first trenches and the plurality of second trenches are filled with a conductive material so as to form a plurality of control gates.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 26, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Xiaobin Wang, Madhur Bobde, Paul Thorup
  • Patent number: 10651750
    Abstract: A constant on-time isolated converter comprises a transformer with a primary side and a secondary side. The primary side is connected to an electronic switch and secondary-side is connected to a load and a processor. The processor is connected to a driver on primary side through at least one coupling element and to the electronic switch. The processor receives an output voltage or an output current across the load generating a control signal accordingly. The driver receives the control signal through the coupling element and accordingly changes the ON/OFF state of the electronic switch, regulating the output voltage and the output current via the transformer, where the duration of the ON/OFF state of the electronic switch is determined between the moment control signal changes from negative to positive and the moment it changes from positive to negative to achieve a high-speed load transient response.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: May 12, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Tien-Chi Lin, Chih-Yuan Liu, Yung-Chuan Hsu, Pei-Lun Huang
  • Patent number: 10644102
    Abstract: A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a combination of shielded trench gate structure and a superjunction structure within an epitaxial layer including alternating n-doped and p-doped columns in an a drift region. In one example the gate trenches are formed in and over n-doped columns that have an extra charge region near and adjacent to the lower portion of the corresponding gate trench. The extra charge is balanced due to the shield electrodes in the gate trenches.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: May 5, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Karthik Padmanabhan, Lingpeng Guan, Madhur Bobde, Jian Wang, Lei Zhang
  • Patent number: 10630080
    Abstract: A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: April 21, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Pei-Lun Huang, Yu-Ming Chen, Tien-Chi Lin, Jung-Pei Cheng, Yueh-Ping Yu, Zhi-Qiang Niu, Xiaotian Zhang, Long-Ching Wang
  • Patent number: 10600727
    Abstract: An intelligent power module (IPM) has a first, second, third and fourth die supporting elements, a first, second, third, fourth, fifth and sixth transistors, a connection member, a low voltage IC, a high voltage IC, a plurality of leads and a molding encapsulation. The first transistor is attached to the first die supporting element. The second transistor is attached to the second die supporting element. The third transistor is attached to the third die supporting element. The fourth, fifth and sixth transistor s are attached to the fourth die supporting element. The low and high voltage ICs are attached to the connection member. The molding encapsulation encloses the first, second, third and fourth die supporting elements, the first, second, third, fourth, fifth and sixth transistors, the connection member and the low and high voltage ICs. The IPM has a reduced thermal resistance of junction-to-case (RthJC) compared to a conventional IPM.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: March 24, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Zhiqiang Niu, Bum-Seok Suh, Jun Lu, Son Tran, Wanki Hong, Guobing Shen, Xiaoguang Zeng, Mary Jane R. Alin
  • Patent number: 10580868
    Abstract: A superjunction power semiconductor device includes a termination region with superjunction structures having higher breakdown voltage than the breakdown voltage of the active cell region. In one embodiment, the termination region includes superjunction structures having lower column charge as compared to the superjunction structures formed in the active cell region. In other embodiments, a superjunction power semiconductor device incorporating superjunction structures with slanted sidewalls where the grading of the superjunction columns in the termination region is reduced as compared to the column grading in the active cell region. The power semiconductor device is made more robust by ensuring any breakdown occurs in the core region as opposed to the termination region. Furthermore, the manufacturing process window for the power semiconductor device is enhanced to improve the manufacturing yield of the power semiconductor device.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: March 3, 2020
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Madhur Bobde, Karthik Padmanabhan, Lingpeng Guan
  • Publication number: 20190385863
    Abstract: A semiconductor device comprising a substrate layer, an epitaxial layer, a dielectric layer, a first aluminum layer, a first titanium interlayer and a second aluminum layer. The first titanium interlayer is disposed between the first aluminum layer and the second aluminum layer. A process for fabricating a semiconductor device comprising the steps of: preparing a semiconductor wafer; depositing a first aluminum layer onto the semiconductor wafer; depositing a first titanium interlayer onto the first aluminum layer; depositing a second aluminum layer onto the first titanium interlayer; applying an etching process so that a plurality of trenches are formed so as to expose a plurality of top surfaces of a dielectric layer; and applying a singulation process so as to form a plurality of separated semiconductor devices.
    Type: Application
    Filed: August 29, 2019
    Publication date: December 19, 2019
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Wei He, Chris Wiebe, Hongyong Xue
  • Publication number: 20190385953
    Abstract: A high voltage (HV) converter implemented on a printed circuit board (PCB) includes a double diffused metal oxide semiconductor (DMOS) package comprising a lead frame and a main DMOS chip. The lead frame includes a gate section electrically connected to a gate electrode of the main DMOS chip, a source section electrically connected to a source electrode of the main DMOS chip and a drain section electrically connected to a drain electrode of the main DMOS chip. The PCB layout includes a large area source copper pad attached to and overlapping the source section of the DMOS package to facilitate cooling and a small area drain copper pad attached to and overlapping the drain section of the DMOS package to reduce electromagnetic interference (EMI) noise.
    Type: Application
    Filed: August 29, 2019
    Publication date: December 19, 2019
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Zhiqiang Niu, Kuang Ming Chang, Lin Chen, Ning Sun, QiHong Huang, Tzu-Hsin Lu
  • Patent number: 10504823
    Abstract: A power semiconductor package has a small footprint. A preparation method is used to fabricate the power semiconductor package. A first semiconductor chip and a second semiconductor chip are attached to a front side and a back side of a die paddle respectively. Conductive pads are then attached to electrodes at top surfaces of the first and second semiconductor chips. It is followed by a formation of a plastic package body covering the die paddle, the first and second semiconductor chips, and the conductive pads. Side surfaces of the conductive pads are exposed from a side surface of the plastic package body.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: December 10, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Hongtao Gao, Jun Lu, Ming-Chen Lu, Jianxin Ye, Yan Huo, Hua Pan
  • Publication number: 20190372463
    Abstract: The invention proposes a system and method for extending the maximum duty cycle of a step-down switching converter to nearly 100% while maintaining a constant switching frequency. The system includes a voltage mode or current mode step-down converter driven by a leading edge blanking (LEB) signal, which operates at the desired switching frequency. More particularly, the LEB signal is connected to a slope generator and/or a current sensing network. In each switching cycle, the LEB signal forces the slope signal and/or current sensing signal to reinitiate, thereby achieving a constant switching frequency and disassociating the switching frequency of the converter from the error voltage VCOMP. Corresponding methods for how to extend the maximum duty cycle of a step-down switching converter while maintaining a constant frequency are also disclosed.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 5, 2019
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventor: Youngbok Kim