Patents Assigned to Alpha and Omega Semiconductor Incorporated
  • Patent number: 10804355
    Abstract: A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.
    Type: Grant
    Filed: January 27, 2019
    Date of Patent: October 13, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Jun Hu, Madhur Bobde, Hamza Yilmaz
  • Patent number: 10777673
    Abstract: A high electron mobility transistor (HEMT) gallium nitride (GaN) bidirectional blocking device includes a hetero-junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The HEMT GaN bidirectional blocking device further includes a first source/drain electrode and a second source/drain electrode disposed on two opposite sides of a gate electrode disposed on top of said hetero-junction structure for controlling a current flow between the first and second source/drain electrodes in the 2DEG layer wherein the gate electrode is disposed at a first distance from the first source/drain electrode and a second distance from the second source/drain electrode and the first distance is different from the second distance.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: September 15, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: David Sheridan
  • Patent number: 10770543
    Abstract: The present invention is directed to a semiconductor chip comprising a high voltage device and a low voltage device disposed thereon. The chip may be formed in several different configurations. For example, the semiconductor chip may include a NPN bipolar transistor, PNP bipolar transistor, a diode, an N channel DMOS transistor and the like. the first doped well being configured as a base of the DMOS transistor, a P channel DMOS transistor and the like. These and other embodiments are described in further detail below.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: September 8, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventor: Hideaki Tsuchiko
  • Patent number: 10763351
    Abstract: Fabricating a semiconductor device comprises: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body in the epitaxial layer; forming a source embedded in the body; forming a contact trench that extends through the source and at least part of the body; disposing an implant at least along a contact trench wall; and disposing an epitaxial enhancement portion below the contact trench and in contact with the implant.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: September 1, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Ji Pan, Anup Bhalla
  • Patent number: 10755931
    Abstract: A semiconductor device includes a superjunction structure formed using simultaneous N and P angled implants into the sidewall of a trench. The simultaneous N and P angled implants use different implant energies and dopants of different diffusion rate so that after annealing, alternating N and P thin semiconductor regions are formed. The alternating N and P thin semiconductor regions form a superjunction structure where a balanced space charge region is formed to enhance the breakdown voltage characteristic of the semiconductor device.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: August 25, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Karthik Padmanabhan, Madhur Bobde, Lingpeng Guan, Lei Zhang, Hamza Yilmaz
  • Patent number: 10686035
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: June 16, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
  • Patent number: 10686062
    Abstract: This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode.
    Type: Grant
    Filed: May 11, 2013
    Date of Patent: June 16, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Anup Bhalla
  • Patent number: 10686056
    Abstract: A semiconductor power device formed in a semiconductor substrate that includes a plurality of trenches formed at a top portion of the semiconductor substrate. The trenches extend laterally across the semiconductor substrate along a longitudinal direction and each trench has a nonlinear portion thus the nonlinear portion has a trench sidewall perpendicular to the longitudinal direction of the trench. A plurality of trench bottom dopant regions are formed below the trench bottom surface. A sidewall dopant region is formed along the perpendicular sidewall wherein the sidewall dopant region extends vertically downward along the perpendicular sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 16, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yangping Ding, Sik Lui, Madhur Bobde, Lei Zhang, Jongoh Kim, John Chen
  • Patent number: 10680097
    Abstract: A semiconductor device, comprising: a substrate; an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; a gate pickup trench in the substrate; a first conductive region and a second conductive region disposed in the gate pickup trench, the first conductive region and the second conductive region being separated by oxide, wherein at least a portion of the oxide surrounding the first conductive region in the gate pickup trench is thicker than at least a portion of the oxide under the second conductive region; and a body region in the substrate.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: June 9, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: John Chen, Il Kwan Lee, Hong Chang, Wenjun Li, Anup Bhalla, Hamza Yilmaz
  • Patent number: 10644118
    Abstract: Embodiments of the present disclosure provide a self-aligned contact for a trench power MOSFET device. The device has a layer of nitride provided over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. Alternatively, the device has an oxide layer over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: May 5, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hongyong Xue, Sik Lui, Terence Huang, Ching-Kai Lin, Wenjun Li, Yi Chang Yang, Jowei Dun
  • Patent number: 10608092
    Abstract: This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.
    Type: Grant
    Filed: December 16, 2017
    Date of Patent: March 31, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, John Chen, Daniel Ng, Wenjun Li
  • Patent number: 10573762
    Abstract: A nitride-based Schottky diode includes a nitride-based semiconductor body, a first metal layer forming the anode electrode, a cathode electrode in electrical contact with the nitride-based semiconductor body, and a termination structure including a guard ring and a dielectric field plate. In one embodiment, the cathode electrode is formed on the front side of the nitride-based semiconductor body, in an area away from the anode electrode and the termination structure. In another embodiment, the dielectric field plate includes a first dielectric layer and a recessed second dielectric layer. In another embodiment, the dielectric field plate and the nitride-based epitaxial layer are formed with a slant profile at a side facing the Schottky junction of the Schottky diode. In another embodiment, the dielectric field plate is formed on a top surface of the nitride-based epitaxial layer and recessed from an end of the nitride-based epitaxial layer near the Schottky junction.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: February 25, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: TingGang Zhu, Anup Bhalla, Ping Huang, Yueh-Se Ho
  • Patent number: 10553714
    Abstract: A trench MOSFET device is fabricated with body source regions that undulate along a channel width direction of the MOSFET device such that the body region and source region have variations in depth along the channel width direction. The undulations increase a channel width of the MOSFET device.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: February 4, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventor: Sik Lui
  • Patent number: 10522666
    Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: December 31, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Anup Bhalla, Madhur Bobde, Yongping Ding, Xiaotian Zhang, Yueh-Se Ho
  • Patent number: 10446545
    Abstract: A bi-directional semiconductor switching device includes first and second vertical field effect transistors (FETs) formed in tandem from a semiconductor substrate. A source for the first FET is on a first side of the substrate and a source for the second FET is on a second side of the substrate opposite the first side. Gates for both the first and second FETs are disposed in tandem in a common set of trenches formed a drift region of the semiconductor substrate that is sandwiched between the sources for the first and second FETs. The drift layer acts as a common drain for both the first FET and second FET.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 15, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventor: Sik Lui
  • Patent number: 10446679
    Abstract: A method for forming a lateral superjunction MOSFET device includes forming a semiconductor body including a lateral superjunction structure and a first column connected to the lateral superjunction structure. The MOSFET device includes the first column to receive current from the channel when the MOSFET is turned on and to distribute the channel current to the lateral superjunction structure functioning as the drain drift region. In some embodiment, the MOSFET device includes a second column disposed in close proximity to the first column. The second column disposed near the first column is used to pinch off the first column when the MOSFET device is to be turned off and to block the high voltage being sustained by the MOSFET device at the drain terminal from reaching the gate structure. In some embodiments, the MOSFET device further includes termination structures for the drain, source and body contact doped region fingers.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: October 15, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Lingpeng Guan, Karthik Padmanabhan, Hamza Yilmaz
  • Patent number: 10439058
    Abstract: A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: October 8, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, Tinggang Zhu
  • Patent number: 10424654
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: September 24, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Wenjun Li, Paul Thorup, Hong Chang, Yeeheng Lee, Yang Xiang, Jowei Dun, Hongyong Xue, Yiming Gu
  • Patent number: 10418899
    Abstract: A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal. The first and second MOS transistors have respective gate terminals coupled to the control terminal to receive a control signal to turn the switch circuit on or off where the control signal transitions from a first voltage level to a second voltage level at a slow rate of change. The first MOS transistor has a first threshold voltage and the second MOS transistor has a second threshold voltage where the first threshold voltage is less than the second threshold voltage.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: September 17, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Sik K. Lui, Daniel S. Ng, Xiaobin Wang
  • Patent number: 10411104
    Abstract: Forming a semiconductor device on a semiconductor substrate having a substrate top surface includes: forming a gate trench extending from the substrate top surface into the semiconductor substrate; forming a gate electrode in the gate trench; forming a curved sidewall portion along at least a portion of a sidewall of the gate trench; forming a body region adjacent to the gate trench; forming a source region embedded in the body region, including disposing source material in a region that is along at least a part of the curved sidewall portion; forming a gate top dielectric layer over the gate electrode and having a top side that is below at least a portion of the source region; and forming a metal layer over at least a portion of a gate trench opening and at least a portion of the source region.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: September 10, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: John Chen