Patents Assigned to Alpha and Omega Semiconductor Incorporated
  • Patent number: 10354990
    Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: July 16, 2019
    Assignee: Alpha and Omega Semiconductor incorporated
    Inventor: Madhur Bobde
  • Patent number: 10333006
    Abstract: A method for forming a nitride-based Schottky diode includes forming a nitride-based epitaxial layer on a front side of a nitride-based semiconductor body; forming a first dielectric layer on the nitride-based epitaxial layer; etching the first dielectric layer and the nitride-based epitaxial layer to the nitride-based semiconductor body to define an opening for an anode electrode of the nitride-based Schottky diode and to form an array of islands of the nitride-based epitaxial layer in the opening, the first dielectric layer having an end that is recessed from an end of the nitride-based epitaxial layer near the opening. In another embodiment, the first dielectric layer and the nitride-based epitaxial layer have a slant profile at a side facing the opening for the anode electrode.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: June 25, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: TingGang Zhu, Anup Bhalla, Ping Huang, Yueh-Se Ho
  • Patent number: 10325908
    Abstract: A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device, comprising a substrate of a first conductivity type, a body region of a second conductivity type, a gate electrode formed in a gate trench extending in the body region and substrate, a lightly doped source region and a heavily doped source region formed in the body region, and a source contact extending to the body region formed in a source contact trench next to the gate trench. The lightly doped source region is extended deeper in the body region than the heavily doped source region. The lightly doped source region is adjacent to the source contact trench. A ballast resistor is formed at the lightly doped source region between the heavily doped source region and the body region and a Schottky diode is formed at a contact between the source contact and the lightly doped source region.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 18, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Sik Lui, Madhur Bobde, Ji Pan
  • Patent number: 10319848
    Abstract: A transistor includes a semiconductor body; a first gate electrode formed on a first portion of the semiconductor body and a second gate electrode formed on a second portion of the semiconductor body. A drain region is formed on a first side of the first gate electrode and a first source region is formed on a second side of the first gate electrode. The drain region is formed on a first side of the second gate electrode and a second source region is formed on a second side of the second gate electrode. A trench is formed in the semiconductor body and positioned in the drain region. A doped sidewall region is formed in the semiconductor body along the sidewall of the trench outside of the trench. The doped sidewall region is in electrical contact with the drain region and forms a vertical drain current path for the transistor.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: June 11, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Hideaki Tsuchiko
  • Patent number: 10297594
    Abstract: A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to gate oxide shell. The ANCTGS forms, together with the source, body, epitaxial region, a MOSFET device in the MOSFET array area. Over MOSFET array area and gate pickup area, a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region. Thus, the patterned metal layer forms, with the MOSFET array and the gate pickup area, self-aligned source and body contacts through the inter-ANCTGS separations.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: May 21, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Yeeheng Lee, Jongoh Kim, Hong Chang
  • Patent number: 10276387
    Abstract: A semiconductor device includes a superjunction structure formed using simultaneous N and P angled implants into the sidewall of a trench. The simultaneous N and P angled implants use different implant energies and dopants of different diffusion rate so that after annealing, alternating N and P thin semiconductor regions are formed. The alternating N and P thin semiconductor regions form a superjunction structure where a balanced space charge region is formed to enhance the breakdown voltage characteristic of the semiconductor device.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: April 30, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Karthik Padmanabhan, Madhur Bobde, Lingpeng Guan, Lei Zhang, Hamza Yilmaz
  • Patent number: 10256236
    Abstract: A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal of the switch circuit, the first and second MOS transistors having respective gate terminals coupled to the control terminal to receive a control signal to turn the first and second MOS transistors on or off. The first MOS transistor is characterized by a first reverse gate-to-drain capacitance (Crss) and the second MOS transistor is characterized by a second Crss that is greater than the first Crss.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: April 9, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Ji Pan, Sik Lui
  • Patent number: 10250152
    Abstract: A flyback converter implements a Forced Zero Voltage Switching (ZVS) timing control by detecting a positive current excursion of the secondary winding current as the synchronous rectifier turn off trigger. The synchronous rectifier switch is turned on near the end of the switching cycle or the on duration is extended to develop a current ripple on the secondary winding current. The control circuit of the flyback converter detects a positive current excursion on the secondary winding current to turn off the synchronous rectifier and to start the next switching cycle. At this point, the voltage across the primary switch has been discharged and the primary switch can be turned on with zero drain-to-source voltage. In other embodiments, zero voltage switching for the off-transition of the primary switch is realized by coupling a capacitor across the primary switch or by coupling a capacitor across the primary winding, or both.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: April 2, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Kuang Ming Chang, Lin Chen, Qihong Huang
  • Patent number: 10243072
    Abstract: A method for forming a lateral superjunction MOSFET device includes forming a semiconductor body including a lateral superjunction structure and a first column connected to the lateral superjunction structure. The MOSFET device includes the first column to receive current from the channel when the MOSFET is turned on and to distribute the channel current to the lateral superjunction structure functioning as the drain drift region. In some embodiment, the MOSFET device includes a second column disposed in close proximity to the first column. The second column disposed near the first column is used to pinch off the first column when the MOSFET device is to be turned off and to block the high voltage being sustained by the MOSFET device at the drain terminal from reaching the gate structure. In some embodiments, the MOSFET device further includes termination structures for the drain, source and body contact doped region fingers.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: March 26, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Lingpeng Guan, Karthik Padmanabhan, Hamza Yilmaz
  • Patent number: 10224411
    Abstract: A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: March 5, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Shekar Mallikarjunaswamy, Francois Hebert
  • Patent number: 10205017
    Abstract: A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer to form a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) that comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate. The drain region interfaces with the body region constituting a junction diode. The drain region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: February 12, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Madhur Bobde
  • Patent number: 10199492
    Abstract: A trench MOSFET device includes a body, region and source region that undulate along a channel width direction of the MOSFET device such that the body region and source region have variations in depth along the channel width direction. The undulations increase a channel width of the MOSFET device.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: February 5, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventor: Sik Lui
  • Patent number: 10199455
    Abstract: A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.
    Type: Grant
    Filed: May 21, 2017
    Date of Patent: February 5, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Jun Hu, Madhur Bobde, Hamza Yilmaz
  • Patent number: 10192982
    Abstract: A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device includes a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each trench has a first dimension (depth), a a second dimension (width) and a third dimension (length). The body region is of opposite conductivity type to the lightly and heavily doped layers. An opening is formed between first and second trenches through an upper portion of the source region and a body contact region to the body region. A deep implant region of the second conductivity type is formed in the lightly doped layer below the body region. The deep implant region is vertically aligned to the opening and spaced away from a bottom of the opening.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: January 29, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Hamza Yilmaz, Daniel Ng, Daniel Calafut, Madhur Bobde, Anup Bhalla, Ji Pan, Yeeheng Lee, Jongoh Kim
  • Patent number: 10177221
    Abstract: This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: January 8, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Anup Bhalla, Madhur Bobde, Tinggang Zhu
  • Patent number: 10170563
    Abstract: This invention discloses a gallium nitride based semiconductor power device disposed in a semiconductor substrate. The power device comprises a termination area disposed at a peripheral area of the semiconductor power device comprises a termination structure having at least a guard ring disposed in a trench filled with doped gallium-based epitaxial layer therein.
    Type: Grant
    Filed: February 9, 2013
    Date of Patent: January 1, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Tinggang Zhu
  • Patent number: 10157984
    Abstract: The present invention is directed to a method for forming multiple active components, such as bipolar transistors, MOSFETs, diodes, etc., on a semiconductor substrate so that active components with higher operation voltage may be formed on a common substrate with a lower operation voltage device and incorporating the existing proven process flow of making the lower operation voltage active components. The present invention is further directed to a method for forming a device of increasing operation voltage over an existing device of same functionality by adding a few steps in the early manufacturing process of the existing device therefore without drastically affecting the device performance.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: December 18, 2018
    Assignee: Alpha & Omega Semiconductor Incorporated
    Inventor: Hideaki Tsuchiko
  • Publication number: 20180323155
    Abstract: A trench-type metal-oxide-semiconductor field-effect transistor (MOSFET) device and a fabrication method are disclosed. A semiconductor substrate of a first conductivity type is provided. A plurality of first trenches arranged side by side in a first stripe layout extending along a first direction in a first preset area of the semiconductor substrate are formed. A plurality of second trenches arranged side by side in a second stripe layout extending along a second direction perpendicular to the first direction in a second preset area of the semiconductor substrate are formed. The plurality of first trenches and the plurality of second trenches are filled with a conductive material so as to form a plurality of control gates.
    Type: Application
    Filed: June 21, 2018
    Publication date: November 8, 2018
    Applicant: Alpha and Omega Semiconductor Incorporated
    Inventors: Xiaobin Wang, Madhur Bobde, Paul Thorup
  • Publication number: 20180323282
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.
    Type: Application
    Filed: June 27, 2018
    Publication date: November 8, 2018
    Applicant: Alpha & Omega Semiconductor, Incorporated
    Inventors: Wenjun Li, Paul Thorup, Hong Chang, Yeeheng Lee, Yang Xiang, Jowei Dun, Hongyong Xue, Yiming Gu
  • Patent number: 10121857
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: November 6, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen