Patents Assigned to ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
  • Patent number: 12027983
    Abstract: A multi-phase current mode hysteretic modulator implements phase current balancing among the multiple power stages using slope-compensated emulated phase current signals and individual phase control signal for each phase. In some embodiments, the slope-compensated emulated phase current signals of all the phases are averaged and compared to the slope-compensated emulated phase current signal of each phase to generate a phase current balance control signal for each phase. The phase current balance control signal is combined with the voltage control loop error signal to generate a phase control signal for each phase where the phase control signals are generated for the multiple phases to control the phase current delivered by each power stage.
    Type: Grant
    Filed: May 13, 2023
    Date of Patent: July 2, 2024
    Assignee: Alpha and Omega Semiconductor International LP
    Inventors: Rhys S. A. Philbrick, Steven P. Laur, Nicholas I. Archibald
  • Patent number: 12015336
    Abstract: A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source section of the elevated section of the lead frame. The semiconductor chip is served as a low side field-effect transistor as a flipped-chip connected to a heat sink by a first thermal interface material. A high side field-effect transistor is connected to the heat sink by a second thermal interface material. The low side field-effect transistor and the high side field-effect transistor are mounted on a printed circuit board.
    Type: Grant
    Filed: September 1, 2023
    Date of Patent: June 18, 2024
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Ziwei Yu, Lin Chen, Zhiqiang Niu
  • Publication number: 20240178785
    Abstract: Apparatus and associated methods relate to a post temperature calibration translation circuit (PTCTC) configured to generate a signal corresponding to a predetermined temperature voltage translation relationship (TVTR). In an illustrative example, the PTCTC may be coupled to a motor controller including a control logic to regulate a power input to a motor based on the TVTR. The PTCTC further includes an input port configured to receive a temperature sensor output based on a predetermined transfer function. At least one analog corrective translation circuit (ACTC), for example, may generate temperature input signals to the motor power controller based on the temperature sensor output. The temperature input signals are generated based on a calibrated transfer function such that the temperature input signals substantially match an output according to the TVTR. Various embodiments may advantageously avoid modification of the control logic when the predetermined transfer function is altered.
    Type: Application
    Filed: November 29, 2022
    Publication date: May 30, 2024
    Applicant: Alpha and Omega Semiconductor International LP
    Inventor: Steven J. Goldman
  • Publication number: 20240146218
    Abstract: Apparatus and associated methods relate to a Source Terminal Replication Compensation Circuit for simulating an accurate fraction of a load current. In an illustrative example, a Source Terminal Replication Compensation Circuit (STRCC) may be connected to a motor driving circuit. The STRCC, for example, may include a simulation transistor configured to have a simulated structure of a main transistor in a motor driving circuit. The STRCC may include, for example, a disturbance rejection module (DRM). The DRM may be connected to a source terminal of the sense transistor, and a source terminal of the main transistor. When the DRM is connected to a current sensing resistor, a sense current is generated as a predetermined fraction of a load current of the motor driving circuit, wherein the predetermined fraction is less than 1%. Various embodiments may advantageously reduce heat dissipations at the current sensor resistor.
    Type: Application
    Filed: October 26, 2022
    Publication date: May 2, 2024
    Applicant: Alpha and Omega Semiconductor International LP
    Inventors: ChengYuan He, Sitthipong Angkititraku, Jian Yin, Lin Chen
  • Publication number: 20240096768
    Abstract: A semiconductor package includes a lead frame, a low side field-effect transistor (FET), a high side FET, a metal clip, and a molding encapsulation. The low side FET is flipped and is attached to a first die paddle of the lead frame. The lead frame comprises one or more voltage input (Vin) leads; a gate lead; one or more switching node (Lx) leads; a first die paddle; a second die paddle; and an end paddle. Each of an exposed bottom surface of the one or more Lx leads is directly connected to an exposed bottom surface of the end paddle. A longitudinal direction of an exposed bottom surface of the gate lead is perpendicular to a longitudinal direction of each of the exposed bottom surface of the one or more Lx leads. An entirely of each of the one or more Vin leads is of the full thickness.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Yan Xun Xue, Lin Chen, Long-Ching Wang, Hui Ye
  • Patent number: 11876456
    Abstract: A controller for a switching regulator receiving an input voltage and generating a regulated output voltage includes a buck control circuit and a boost control circuit. The controller activates the buck control circuit to generate the regulated output voltage having a first voltage value less than the input voltage. The controller activates the boost control circuit to return charges stored on the output capacitor at the output node to the input node, thereby driving the regulated output voltage to a second voltage value lower than the first voltage value. In some embodiments, in response to a command instructing the controller to allow the output voltage to decay, the controller operates in the boost mode using the boost control circuit to recycle the stored charge at the output node while ramping down the output voltage.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: January 16, 2024
    Assignee: Alpha and Omega Semiconductor International LP
    Inventors: Nicholas I. Archibald, Steven P. Laur, Rhys S. A. Philbrick
  • Patent number: 11869967
    Abstract: An improved inverted field-effect-transistor semiconductor device and method of making thereof may comprise a source layer on a bottom and a drain disposed on a top of a semiconductor substrate and a vertical current conducting channel between the source layer and the drain controlled by a trench gate electrode disposed in a gate trench lined with an insulating material. A heavily doped drain region is disposed near the top of the substrate surrounding an upper portion of a shield trench and the gate trench. A doped body contact region is disposed in the substrate and surrounding a lower portion of the shield trench. A shield electrode extends upward from the source layer in the shield trench for electrically shorting the source layer and the body region wherein the shield structure extends upward to a heavily doped drain region and is insulated from the heavily doped drain region to act as a shield electrode.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: January 9, 2024
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Sik Lui, Madhur Bobde, Lingpeng Guan, Lei Zhang
  • Patent number: 11863057
    Abstract: Apparatus and associated methods relate to dynamic bandwidth control of a variable frequency modulation circuit by selective contribution of a crossover frequency tuning engine (XFTE) in response to a transient in a switching frequency. In an illustrative example, the XFTE may generate a transient control signal (Ctrans) in response to a transient in a control output signal (Cout) indicative of switching frequency and received from a feedback control circuit. The XFTE may generate Ctrans, for example, according to a predetermined relationship between a crossover frequency and the switching frequency of the modulation circuit. The feedback control circuit may, for example, generate Cout from a predetermined reference and a control input signal. Cout may, for example, correspond to a pulse-width modulated output delivered to a load through an inductor. Various embodiments may advantageously increase the effective bandwidth of the modulation circuit while maintaining desired frequency response characteristics.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: January 2, 2024
    Assignee: Alpha and Omega Semiconductor International LP
    Inventor: Chris M. Young
  • Publication number: 20230420340
    Abstract: A semiconductor package includes a lead frame, a chip, and a molding encapsulation. The lead frame comprises a die paddle, a first plurality of leads, additional one or more leads, a second plurality of leads, a first tie bar, a second tie bar, a third tie bar, and a fourth tie bar. A respective end surface of each lead of the first plurality of leads, the additional one or more leads, and the second plurality of leads is plated with a metal. A respective end surface of the first tie bar, the second tie bar, the third tie bar, and the fourth tie bar is not plated with the metal. A method for fabricating a semiconductor package includes the steps of providing a lead frame array, mounting a chip, forming a molding encapsulation, applying a trimming process, applying a plating process, and applying a singulation process.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 28, 2023
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Yan Xun Xue, Madhur Bobde, Long-Ching Wang, Xiaoguang Zeng
  • Publication number: 20230420362
    Abstract: A semiconductor package comprises a lead frame, a low side metal-oxide-semiconductor field-effect transistor (MOSFET), an E-fuse MOSFET, a high side MOSFET, a metal connection, a gate driver, an E-fuse IC, and a molding encapsulation. A buck converter comprises a smart power stage (SPS) network and an E-fuse solution network. The SPS network comprises a high side switch, a low side switch, and a gate driver. A drain of the low side switch is coupled to a source of the high side switch via a switch node. The gate driver is coupled to a gate of the high side switch and a gate of the low side switch. The E-fuse solution network comprises a sense resistor, an E-fuse switch, an E-fuse integrated circuit (IC), and an SD circuit.
    Type: Application
    Filed: September 5, 2023
    Publication date: December 28, 2023
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventor: Prabal Upadhyaya
  • Publication number: 20230412070
    Abstract: A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source section of the elevated section of the lead frame. The semiconductor chip is served as a low side field-effect transistor as a flipped-chip connected to a heat sink by a first thermal interface material. A high side field-effect transistor is connected to the heat sink by a second thermal interface material. The low side field-effect transistor and the high side field-effect transistor are mounted on a printed circuit board.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 21, 2023
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Ziwei Yu, Lin Chen, Zhiqiang Niu
  • Patent number: 11848608
    Abstract: A control circuit for controlling a switching regulator includes a timer, a comparator, a driver circuit and a controller. The timer generates an input signal indicative of whether a predetermined amount of time has elapsed since an activation of a drive signal. The comparator is configured to compare a feedback voltage with a reference voltage to generate a comparison signal. The driver circuit is controlled by a control signal to generate the drive signal according to one of the input signal and the comparison signal. The control signal indicates whether a mode is enabled. When the mode is enabled, the driver circuit is configured to generate the drive signal according to the input signal. The controller is configured to, in response to an activation of the input signal, generate the control signal according to a result of a comparison of the feedback voltage with another reference voltage higher than the reference voltage.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: December 19, 2023
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Chi-Kuang Chang, Cheng-Hsiung Tsai
  • Patent number: 11809249
    Abstract: A port controller circuit is configured to control power transfer on a power path between a first terminal and a second terminal. The controller circuit includes first and second transistors connected in series between the first terminal and the second terminal, a control terminal of the first transistor receiving a first gate voltage and a control terminal of the second transistor receiving a second gate voltage. A first gate voltage control circuit generates the first gate voltage driving the control terminal of the first transistor and regulates the first gate voltage to keep the first transistor turned on. In response to the first gate voltage control circuit regulating the first gate voltage to a voltage value less than a first voltage level, the first gate voltage control circuit asserts a first signal to indicate a fault condition at the first transistor.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: November 7, 2023
    Assignee: Alpha and Omega Semiconductor International LP
    Inventor: Michael Scheel
  • Patent number: 11798882
    Abstract: A semiconductor package comprises a lead frame, a low side metal-oxide-semiconductor field-effect transistor (MOSFET), an E-fuse MOSFET, a high side MOSFET, a metal connection, a gate driver, an E-fuse IC, and a molding encapsulation. A buck converter comprises a smart power stage (SPS) network and an E-fuse solution network. The SPS network comprises a high side switch, a low side switch, and a gate driver. A drain of the low side switch is coupled to a source of the high side switch via a switch node. The gate driver is coupled to a gate of the high side switch and a gate of the low side switch. The E-fuse solution network comprises a sense resistor, an E-fuse switch, an E-fuse integrated circuit (IC), and an SD circuit.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: October 24, 2023
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventor: Prabal Upadhyaya
  • Publication number: 20230335474
    Abstract: A power module includes a lead frame, a substrate mounted on the lead frame, a first anchor pad, a second anchor pad, a plurality of die pads, and a plurality of transistor dies. The lead frame includes a first lead frame anchored bar attached to the first anchor pad, and a second lead frame anchored bar attached to the second anchor pad. The power module may include a single control IC or two or more control ICs. For the case including a single control IC, the singe control IC controls a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. For the case including two control ICs, a low voltage IC controls a first transistor, a second transistor, and a third transistor and the high voltage IC controls a fourth transistor, a fifth transistor, and a sixth transistor.
    Type: Application
    Filed: April 18, 2022
    Publication date: October 19, 2023
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Zhiqiang Niu, Bum-Seok Suh, Junho Lee, Jong-Mu Lee, Jun Lu, Xiaorong Ge
  • Patent number: 11784141
    Abstract: A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of providing a device wafer; providing a supporting wafer; attaching the supporting wafer to the device wafer via an adhesive layer; and applying a singulaton process so as to form a plurality of semiconductor packages.
    Type: Grant
    Filed: October 5, 2022
    Date of Patent: October 10, 2023
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Jun Lu, Long-Ching Wang, Madhur Bobde, Bo Chen, Shuhua Zhou
  • Patent number: 11774296
    Abstract: A method and device for temperature monitoring of a power transistor formed in a semiconductor die comprising are disclosed. A side of a temperature-sensing resistor disposed in the semiconductor die is coupled to a voltage input side of the power transistor. A controller coupled to a second side of the temperature-sensing resistor is configured to detect a voltage across the resistor and trigger a temperature related corrective action using the detected voltage.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: October 3, 2023
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Zhenyu Wang, Jian Yin, Lingpeng Guan, Sitthipong Angkititrakul, Christopher Ben Bartholomeusz, Xiaobin Wang
  • Patent number: 11776994
    Abstract: A silicon carbide MOSFET device and method for making thereof are disclosed. The silicon carbide MOSFET device comprises a substrate heavily doped with a first conductivity type and an epitaxial layer lightly doped with the first conductivity type. A body region of a second conductivity type opposite the first is formed in epitaxial layer and an accumulation mode region of the first conductivity type is formed in the body region and an inversion mode region of the second conductivity type formed in the body region. The accumulation mode region is located between the inversion mode region and a junction field effect transistor (JFET) region of the epitaxial layer.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: October 3, 2023
    Assignee: Alpha and Omega Semiconductor International LP
    Inventors: David Sheridan, Arash Salemi, Madhur Bobde
  • Publication number: 20230307325
    Abstract: A semiconductor device comprises a semiconductor substrate, a plurality of metal layers, an adhesive layer, a compound layer, and a plurality of contact pads. A thickness of the semiconductor substrate is in a range from 15 ?m to 35 ?m. A thickness of the compound layer is larger than the thickness of the semiconductor substrate. A coefficient of thermal expansion of the compound layer is less than or equal to 9 ppm/° C. A glass transition temperature of the compound layer is larger than 150° C. The plurality of metal layers comprises a first titanium layer, a first nickel layer, a silver layer, a second nickel layer, and a metallic layer. In a first example, the metallic layer is a second titanium layer. In a second example, the metallic layer is a Titanium Nitride (TiN) layer.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Lin Lv, Shuhua Zhou, Long-Ching Wang, Jun Lu
  • Publication number: 20230308018
    Abstract: A control circuit for controlling a switching regulator includes a timer, a comparator, a driver circuit and a controller. The timer generates an input signal indicative of whether a predetermined amount of time has elapsed since an activation of a drive signal. The comparator is configured to compare a feedback voltage with a reference voltage to generate a comparison signal. The driver circuit is controlled by a control signal to generate the drive signal according to one of the input signal and the comparison signal. The control signal indicates whether a mode is enabled. When the mode is enabled, the driver circuit is configured to generate the drive signal according to the input signal. The controller is configured to, in response to an activation of the input signal, generate the control signal according to a result of a comparison of the feedback voltage with another reference voltage higher than the reference voltage.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Chi-Kuang Chang, Cheng-Hsiung Tsai