Abstract: A central processor architecture implementating a deterministic, digit based, subterm computation and selective subterm combination early condition code analysis mechanism to provide for the early determination of the condition code that will be returned upon normal execution of a condition code setting instruction is described. The early condition code is returned sufficiently early to be combined with a branch mask to substantially reduce if not eliminate the need to interlock an immediately following conditional branch instruction. A wide variety of condition code setting instructions are handled by the deterministic condition code analysis mechanism of the present invention by implementing the mechanism to determine condition codes by the generation of digit subterms of the operand data accompanying condition code setting instruction and then combining the digit subterms in a predetermined manner selected based on the specific condition code setting instruction being executed.

Abstract: A method for providing void-free low-electrical-resistance conductive cores in vias having an aspect ratio of greater than approximately 6 includes the steps of providing a conductive thixotropic paste on the top surface of a substrate having vias provided therein, applying pressure to the paste and concurrently applying pressure to the paste and bottom surface of the substrate to force the thixotropic paste into the vias. Vibratory motion may also be applied to the substrate and paste concurrently with the application of pressure and vacuum. The paste is then dried in a vacuum, and subsequently sintered in a two-step process including a slow ramp up to temperature to allow the paste to outgas followed by a high temperature treatment.

Abstract: A process for preparing a polyimide by reaction of a diamine and a tetracarboxylic dianhydride to obtain a polyamide acid and subjecting the polyamide acid to conversion into a polyimide thermally or chemically. The reaction in the process is carried out in the presence of at least one dicarboxylic anhydride selected from the group consisting of aliphatic dicarboxylic anhydrides and aromatic dicarboxylic anhydrides, and the amount of the tetracarboxylic dianhydride is in the range of from 0.9 to 1.0 mole per mole of the diamine and the amount of the dicarboxylic anhydride is in the range of from 0.001 to 1.0 mole per mole of the diamine. The resultant polyimides exhibit good thermal stability at high temperatures and good forming processability even at low temperatures.

Abstract: Described is a digital phase lock device comprising a feedback loop having a plurality of delay elements and a selector. The delay elements delay a sampling signal into signals having different time delay values relative to the sampling signal. These delay signals are compared with a periodic target signal whereby one of them is selected as the next sampling signal. As a result, the sampling signal tracks the periodic signal.

Abstract: In a data processing system in which a processor has a cache receiving data staged from at least two main memories. Performance is enhanced by providing an indicator identifying the main memory from which data is staged. When data in the cache is destaged, the indicator is used to direct the destaged data to the proper main memory. If an error occur in the indicator, the data will be destaged to each main memory where a check is made on the address of the data to determine whether the main memory is the source of the destaged data. The data is stored in a main memory only if the memory is the source thereof.

Abstract: A method and apparatus for providing arbitration between and serialization of plural processors in a multiprocessor system comprising, in each processor, a delay network, a priority circuit, a REQUEST generator, an ORDER generator, a serialization program, an ACK generator and an ACK receiver. In operation, the delay network insures that simultaneously generated REQUESTS received from plural processors are received by the priority circuit at the same time. A processor awarded priority issues an ORDER to the other processors and thereafter drops its REQUEST to allow an award of priority to another processor. An ACK is received by the ORDER issuing processor from each processor when it executes the ORDER. The ORDER issuing processor then completes the task which gave rise to the ORDER. To conserve processing time, priority awards may be made before previously issued ORDERS are completed.

Abstract: In a data processing system having a main processor and a plurality of service processors providing service functions to the main processor, including a first service processor providing primary service functions and a second service processor providing secondary service functions. The main processor performs failure detection on the first processor, and upon the detection of a failure, initiates a switch between the first and the second service processors.

Abstract: A pin grip array zero insertion force connector has 10,000 or more normally closed contacts provided in rows on a motherboard. Alternating rows of contacts respectively include first and second type contacts, and drawbars are provided between the rows of contacts. Alternate drawbars are caused to slide in opposite directions, thereby engaging the drawbars with one of the two tines of each contact in the rows of contacts on either side of the drawbar. An actuator mechanism is provided at each end of the rows of contacts and drawbars to engage and slide the drawbars. To reduce the force necessary to operate each actuator mechanism, the actuator mechanisms may be divided into subactuator mechanisms which are individually actuated. The drawbars comprises a drawbar support strip which engages the actuator mechanisms and an interposer body molded to retaining tabs on the drawbar support strip.

Abstract: An apparatus and method for use in improving cache storage unit utilization during an interlock of an instruction pipeline generates a control signal during one cycle of the interlock if the interlocked instruction may require storage unit management work. In response to the control signal, selector control logic in the storage unit generates a priority signal indicating the interlocked instruction for selection by the storage unit for processing. In response to the control signal and the priority signal, the cache management logic is used during the interlock on the interlocked instruction to prepare for supplying needed data when the interlock is released.

Abstract: A queue buffer used for the controlled buffering and transferal of data between a cache memory of a central processor unit and a mainstore memory unit. The queue buffer of the present invention preferably includes a buffer memory for the queued storage of data and a controller for directing the nominally immediate acceptance and storage of data received direct from a cache memory and for the nominally systematic background transfer of data from the queue buffer to the mainstore memory unit. This nominal prioritization of memory transfers with respect to the queue buffer memory allows data move-in requests requiring data from the main storage unit to proceed while required move-out data is moved from a cache memory immediately to the buffer queue memory.

Abstract: In a data processing system that stores a first and second version of a given data set, a method for synchronizing the first and second versions comprises steps of maintaining a sync-complete control field and a sync-in-progress control field in the inode of each of the first and second versions. Write accesses to the versions are modified so that the sync-complete control field and the sync-in-progress control field are cleared in response to any change in the associated version. The sync-complete control bits for the first and second versions are tested, and if either or both are cleared, then the sync-in-progress control field associated with a select source version is set. Next, a copy of the source version is transferred to a temporary file.

Abstract: In a data processing system including a pipelined instruction execution unit and a pipelined high speed cache, a storage queue consisting of a set of FIFO registers and associated support logic handles transfer of data from the pipeline instruction execution unit to the high speed cache. When a store request flow from the instruction execution pipeline is forwarded to the high speed cache, instead of placing the data directly into the high speed cache, the starting address, length of store and data to be stored are placed into one of the store queue registers. The instruction execution unit sees the store request as completed and continues processing even though data has not been physically placed in the high speed cache. The write to the high speed cache is finished in the background at a later time during an unused storage pipeline cycle in the high speed cache.

Abstract: A phase-locked loop with redundant reference input signals compares each reference input signal to the loop feedback signal to generate corresponding phase correction signals. In response to a reference select signal, one of the phase correction signals is selected for supply as a loop correction signal. The loop correction signal is supplied through a filter as a control signal to a VCO. Phase and frequency detectors are included, each detector receiving a corresponding reference input signal and connected to receive the loop feedback signal for generating a phase correction signal indicating the phase and frequency difference between the corresponding reference input signals and the output signal. Also, a selector is provided in communication with each of the detectors that selects one of the phase correction signals in response to the reference select signal as the loop correction signal.

Abstract: In a pipeline data processing machine having a first unit for execution of instructions running according to a first pipeline and a second unit for storing data from a plurality of ports running according to a second pipeline, the first unit having a result register for holding results including data and address information of a flow of the first pipeline, the present invention provides an apparatus for transferring results in the result register to the second unit. A plurality of registers connected to the result register, each storing the result from at least one flow of the first pipeline and storing control information is provided. Further, a controller in communication with the second unit and the plurality of ports responsive to the control information and a flow of the second pipeline is included for selecting one of the plurality of ports in a first-in, first-out queue as a port to the second unit and for updating the control information.

Abstract: An interlock of an instruction processing pipeline in a data processing system responsive to the validity of the pipeline stages within the instruction unit pipeline under microprogram control, is provided. Thus, a microprogram can provide for the release of a particular pipeline stage based on a selected characteristic of the valid signals generated by other stages of the pipeline. An interlock control signal is generated by a decode of a field in a microinstruction stored in a control store RAM or through hardwired decoding.

Abstract: A circuit responsive to a switching signal for dynamically changing the frequency source of a system clock. The circuit allows addition of new frequency sources without substantial changes to the circuit because its circuitry for detecting an inactive cycle period of the new frequency source is asynchronous (i.e. not clocked by the new frequency source).

Abstract: Bypassing of data from a main storage unit to an instruction and operand processing unit around an intermediate storage unit improves performance in a data processing system. The instruction and operand processing unit supplies requests for operands to the intermediate storage unit or cache. If the line is missing from the cache, the request operand is retrieved from the main storage unit. A bypass data path is connected between the main storage unit, prior to error detecting means in the cache, and the instruction and operand processing unit for transferring requested operands to the instruction and operand processing unit directly. Control, coupled to receive requests for operands and to the instruction and operand processing unit, signals the instruction and operand processing unit to receive the requested operands from the bypass data path when the data includes a requested operand.

Abstract: The present invention provides an apparatus for reporting errors in data stored in a memory apparatus of a data processor, comprising: first means for storing multiple digital first signals; second means for storing said multiple digital first signals and adapted for storing at least one digital second signal; third means for transmitting said multiple digital first signals substantially from said first means to said second means; fourth means for providing said at least one digital second signal, in the course of the transmitting of said first signals by said third means, in response to an occurrence of one or more errors in one or more of said multiple digital first signals; fifth means for transmitting said multiple digital first signals substantially from said second means to said first means; and sixth means adapted for receiving said at least one digital second signal in the course of the transmitting of said multiple digital first signals by said fifth means and for providing at least one third signal

Abstract: A three-dimensional microelectronic package for semiconductor chips includes a plurality of cavity wafers, each cavity wafer having a plurality of cavities and tunnels for providing coolant to the cavities, and a plurality of wafer packs provided between adjacent, stacked cavity wafers, each cavity wafer and wafer pack having conductive paths. Chip carriers for housing semiconductor chips are attached to portions of the wafer packs corresponding to the positions of the cavities in the cavity wafers. The chip carriers electrically interconnect the semiconductor chips with the connective paths of the wafer packs, and, through the wafer packs, the cavity wafers. The chip carriers also provide a medium for exchanging heat between the semiconductor chips and the coolant flowing to the cavities in the cavity wafers. Conductive paths provided in the cavity wafers electrically interconnect the various wafer packs.

Abstract: A clock control apparatus that stops a system clock in a high performance high speed computer a determined number of system clock cycles after the generation of the clock control signal by a digital computer. The apparatus receives a basic clock signal and the clock control signal and generates a system clock for the system. The system clock includes a normal system clock signal and at least one early system clock signal. The basic clock is provided through a delay tap generating a normal basic clock signal and at least one early basic clock signal. In addition, a control state machine receiving the normal basic clock signal and the at least one early basic clock signal and responsive to the clock control signal is provided for starting and stopping the system clock. The clock control signal is synchronized with the earliest system clock and supplied to the clock control state machine.