Abstract: A method and apparatus for reinforcing the solder connections between a semiconductor device and a substrate includes the provision of a rigid frame having a central opening through it, a planar top surface, a bottom surface opposite and parallel to the top surface, and a thickness between the two surfaces to equal to the height of the solder connections. The top surface of the frame is attached to the bottom surface of the semiconductor device at the peripheral edges thereof and outside of a plurality of input/output terminals thereon. The bottom surface of the frame is attached to the top surface of the substrate. The frame reinforces the solder connections between a C4-mounted semiconductor die or a C5-mounted semiconductor package and a substrate against the stresses acting on the connections with bending of the PCB.

Abstract: A wafer is singulated from the back-side surface of the wafer using laser ablation, thus protecting the front-side surface of the wafer and, more particularly, the integrated circuits and/or functional units on the front-side surface. Since, according to the invention, no saw blade is used, the width of the scribe lines does not need to be any larger than the width of the beam from the laser plus some minimal tolerance for alignment. As a result, using the invention, the width of scribe lines is on the order of twenty-four times smaller than the width of scribe lines required by the prior art methods.

Abstract: Semiconductor packages having a thin structure capable of easily discharging heat from a semiconductor chip included therein, and methods for fabricating such semiconductor packages, are disclosed.

Abstract: A thin image sensor package includes an image sensor having an active area which is responsive to radiation. The image sensor is mounted to a substrate which is transparent to the radiation. The image sensor is mounted such that the active area of the image sensor faces the substrate. Of importance, the substrate serves a dual function. In particular, the substrate is the window which covers the active area of the image sensor. Further, the substrate is the platform upon which the image sensor package is fabricated. As a result, the image sensor package is thin, lightweight and inexpensive to manufacture.

Abstract: A thin, thermally efficient, lead frame-type of semiconductor package incorporating multiple dies includes a plurality of electrically conductive leads held together in a spaced, planar relationship about a central opening defined by the leads, and a plurality of thick, plate-like heat sinks supported within the opening such they are generally coplanar with each other, parallel to the plane of the leads, and electrically isolated from the leads and each other. Each of the heat sinks has a lower surface that can be exposed through the outer surface of a molded resin envelope encapsulating the package for the efficient dissipation of heat therefrom, and an upper surface having a recess formed into it. A semiconductor die is mounted in each of the recesses with its back surface in electrical connection with the floor of the recess.

Abstract: A method of fabricating a semiconductor package is provided, which realizes a small-size semiconductor package without performance deterioration, to meet a tendency to miniaturization of electronic products in which semiconductor packages are mounted, such as communication apparatus and computer, provides a new type of compact multi-pin semiconductor package as large as a semiconductor chip mounted thereon, and accomplishes a semiconductor package having multi-function to minimize its mounting area on an electronic product, resulting in minimizing of the products.

Abstract: Image sensor packages are fabricated simultaneously to minimize the cost associated with each individual image sensor package. To fabricate the image sensor packages, windows are molded in molding compound to form a molded window array. A substrate includes a plurality of individual substrates integrally connected together in an array format. Image sensors are attached and electrically connected to corresponding individual substrates. An adhesive layer attaches the molded window array to the substrate. The substrate and attached molded window array are singulated into a plurality of individual image sensor packages.

Abstract: A novel, moisture-resistant integrated circuit chip package is disclosed. In one embodiment, the integrated circuit chip package includes a rigid substrate having a chip side and a backside. A first conductive layer is formed on the chip side of the substrate, and has a pattern forming conductive traces. A first soldermask layer is formed on the chip side of the substrate. The first soldermask layer directly contacts the first conductive layer. The first soldermask layer has at least one opening formed therein. A first contact layer is formed over the first conductive layer in the opening of the first soldermask layer. A second conductive layer is formed on the backside of the substrate. A second soldermask layer is formed on the back side of the substrate and has at least one opening formed therein. A second contact layer overlies the second conductive layer in the opening of the second soldermask layer.

Abstract: A semiconductor package and a method of making the package are disclosed. The package includes a semiconductor chip having first surface with a conductive pad thereon. A first end of a bond wire is connected to each of the pads. Encapsulant covers the fist surface of the chip, the pads, and the bond wires, and forms side surfaces of the package. A second end of the bond wires is exposed at a side surface of the package. Making the package includes providing a wafer including a plurality of semiconductor chip units. Each chip unit has a plurality of conductive pads at a first surface of the wafer. A bond wire is electrically connected between each pad of each semiconductor chip unit and a pad of at least one adjacent semiconductor chip unit of the wafer. An encapsulant is applied onto the first surface of the wafer so as to completely cover the bond wires and pads of the semiconductor units.

Abstract: A package includes both a flip chip mounted active Chip component and a passive chip component. The flip chip bumps between the bond pads of the active chip component and the substrate are low impedance. Further, by mounting the active chip component as a flip chip, the area on the substrate occupied by the active chip component is approximately equal to the area of the active chip component.

Abstract: A semiconductor package is disclosed that bonds a semiconductor chip to a leadframe using a flip chip technology. An exemplary semiconductor package includes a semiconductor chip having a plurality of input-output pads at an active surface thereof. A plurality of leads are superimposed by the bond pads and active surface of the semiconductor chip. The leads have at least one exposed surface at a bottom surface of the package body. A plurality of conductive connecting means electrically connect the input-output pads of the chip to the leads. A package body is formed over the semiconductor chip and the conductive connecting means. The bottom surface portions of the leads are exposed to the outside.

Abstract: Electrically conductive interior traces and exterior traces are formed on interior and exterior surfaces, respectively, of a window. The interior traces are electrically connected to the exterior traces by electrically conductive vias extending through the window. To mount the window to an image sensor, the interior traces are aligned with bond pads on a front surface of the image sensor. Flip chip bumps are formed between the interior traces and the bond pads thus mounting the window to the image sensor. A sealer is applied to form a seal between the window and the image sensor and to protect an active area of the image sensor.

Abstract: In a method of fabricating a semiconductor device, a plurality of MOS devices are formed on a semiconductor substrate each with a source, a drain, and a gate electrode. A first insulating layer is formed on the semiconductor substrate with the MOS devices. A moat pattern is formed on the first insulating layer such that the portions of the first insulating layer placed at device isolation areas are exposed to the outside. Trenches are formed at the semiconductor substrate through etching the first insulating layer and the underlying semiconductor substrate using the moat pattern as a mask. The semiconductor substrate is partially etched by a predetermined depth. The trenches are filled up through forming a second insulating layer on the etched portions of the semiconductor substrate, and on the first insulating layer.

Abstract: This invention provides a method for making a semiconductor package with stacked dies that substantially reduces risk of fracturing of the dies and prevents breakage of the wire bonds caused by wire sweep. One embodiment of the method includes the provision of a substrate and a pair of semiconductor dies, each having opposite top and bottom surfaces and a plurality of wire bonding pads around the peripheries of their respective top surfaces. One die is attached and wire bonded to a top surface of the substrate. A measured quantity of an uncured, fluid adhesive is dispensed onto the top surface of the first die, and the adhesive is squeezed out to the edges of the dies by pressing the bottom surface of the second die down onto the adhesive until the two dies are separated by a layer of the adhesive. The adhesive is cured and the second die is wire bonded to the substrate. A bead of an adhesive is dispensed around the periphery of the dies such that it covers the wire bonds and bonding pads on the second die.

Abstract: A method for making low cost chip size semiconductor packages (“CSPs”) includes preparing a substrate having a first surface with metal pads and lands thereon, and an opposite second surface having openings in it through which the lands are exposed. A solder mask is formed over the first surface of the substrate, and has apertures in it through which the metal pads are exposed. At least one vent opening is formed through the substrate and solder mask. A semiconductor die is electrically connected to the substrate through the apertures in the solder mask using the “flip chip” connection method. A body of an insulative plastic material is formed on the surface of the solder mask that simultaneously overmolds the die and underfills the space between the solder mask and the die in a single step. Solder balls are attached to the lands through the openings in the second surface of the substrate to serve as package input/output terminals.

Abstract: A method of forming a trench for semiconductor device isolation includes the steps of making a trench at a device isolation area of a silicon wafer by etching the silicon wafer and within through a mask pattern, forming a liner oxide on the silicon wafer with the trench through thermal oxidation, forming a nitride on the liner oxide through low pressure chemical vapor deposition, and anisotropically dry-etching the nitride such that the nitride is left only at the sidewalls of the trench. A trench-filling oxide is then deposited onto the entire surface of the silicon wafer through high pressure chemical vapor deposition, and annealed. The trench-filling oxide is planarized through chemical mechanical polishing until the top surface of the trench-filling oxide is positioned slightly over the liner oxide on the silicon wafer. The silicon wafer is then wet-cleaned, and thermally oxidized such that a pad oxide is grown at the surface of the silicon wafer.

Abstract: The present invention includes a package for housing an integrated circuit device. The present invention also includes leadframes and methods for making such packages. In one embodiment, the package includes an integrated circuit device on a metal die pad. A metal ring is between the die pad and leads and surrounds the die pad. The ring is connected to the die pad by a nonconductive adhesive tape. Encapsulant material covers the entire structure, except for portions of the leads. The ring is electrically connected to a lead identified for connection to an external power voltage supply. The ring in turn is electrically connected to a power voltage input pad on the integrated circuit device. The potential of the die pad may float, or the die pad may be electrically connected through a lead to an external ground voltage. The package is made from a leadframe that has a die pad, a metal ring between the die pad and radiating leads, and a nonconductive adhesive tape that connects the ring to the die pad.

Abstract: A low-cost printed circuit board for a semiconductor package having the footprint of a ball grid array package has an integral heat sink, or “slug,” for the mounting of one or more semiconductor chips, capable of efficiently conducting away at least five watts from the package in typical applications. It is made by forming an opening through a sheet, or substrate, of B-stage epoxy/fiberglass composite, or “pre-preg,” then inserting a slug of a thermally conductive material having the same size and shape as the opening into the opening. The slug-containing composite is sandwiched between two thin layers of a conductive metal, preferably copper, and the resulting sandwich is simultaneously pressed and heated between the platen of a heated press.

Abstract: A lead frame such as a normal or inverted lead frame includes an unsymmetrical part such as a gate. A clamp, for clamping the lead frame during wire bonding, includes an observation hole. The unsymmetrical part of the lead frame is visible through the observation hole. A lead eye box and a lead eye point are set on the unsymmetrical part through the observation hole. The picture inside the lead eye box is captured and compared to a control picture. Setting the lead eye box and the lead eye point on the unsymmetrical part through the observation hole allows detection of when the lead frame is inadvertently rotated at prescribed angles or when a normal lead frame and an inverted lead frame are inadvertently mixed.

Abstract: Methods of making integrated circuit device packages and substrates for making the packages are disclosed. An embodiment of a method of making a substrate includes providing an unpatterned sheet of polyimide material having a first surface and an opposite second surface. A planar metal layer is attached to the second surface of the polyimide sheet. The metal layer is patterned to form an array of package sites, with each site including a planar die pad and planar leads. Apertures are formed through the polyimide sheet, either before or after attaching the metal layer. Each aperture is juxtaposed with a lead allowing access thereto. A method of making a package using the substrate includes mounting an integrated circuit device above the die pad (e.g., on the substrate or on the die pad through an aperture in the substrate). Bond wires are connected between the integrated circuit device and the leads through the apertures.