Abstract: Compressive stress in a film of a semiconductor device may be controlled utilizing one or more techniques, employed alone or in combination. A first set of embodiments increase silicon nitride compressive stress by adding hydrogen to the deposition chemistry, and reduce defects in a device fabricated with a high compressive stress silicon nitride film formed in the presence of hydrogen gas. A silicon nitride film may comprise an initiation layer formed in the absence of a hydrogen gas flow, underlying a high stress nitride layer formed in the presence of a hydrogen gas flow. A silicon nitride film formed in accordance with an embodiment of the present invention may exhibit a compressive stress of 2.8 GPa or higher.

Abstract: A method of polishing a substrate includes holding the substrate on a polishing pad with a polishing head, wherein the polishing pad is supported by a platen, creating relative motion between the substrate and the polishing pad to polish a side of the substrate, generating a light beam and directing the light beam towards the substrate to cause the light beam to impinge on the side of the substrate being polished. Light reflected from the substrate is at a detector to generate an interference signal. A measure of uniformity is computed from the interference signal.

Abstract: A method for supporting a glass substrate comprising providing a substrate support having an aluminum body, a substrate contact area formed on the surface of the substrate support, wherein the process of forming the substrate contact area comprises forming an anodization layer on a surface region of the aluminum body, the coating having a thickness of between about 0.3 mils and about 2.16 mils, wherein the surface region substantially corresponds to the substrate contact area, and preparing the anodization layer disposed over the surface region to a surface roughness between about 88 micro-inches and about 230 micro-inches, followed by anodizing the substrate surface to said thickness, positioning the substrate support adjacent a substrate processing region in a substrate processing chamber, wherein the substrate contact area is adjacent the substrate processing region, positioning the glass substrate on the substrate contact area.

Abstract: Embodiments of the invention provide an improved process for depositing tungsten-containing materials. The process utilizes soak processes and vapor deposition processes to provide tungsten films having significantly improved surface uniformity while increasing the production level throughput. In one embodiment, a method is provided which includes depositing a tungsten silicide layer on the substrate by exposing the substrate to a continuous flow of a silicon precursor while also exposing the substrate to intermittent pulses of a tungsten precursor. The method further provides that the substrate is exposed to the silicon and tungsten precursors which have a silicon/tungsten precursor flow rate ratio of greater than 1, for example, about 2, about 3, or greater. Subsequently, the method provides depositing a tungsten nitride layer on the tungsten suicide layer, depositing a tungsten nucleation layer on the tungsten nitride layer, and depositing a tungsten bulk layer on the tungsten nucleation layer.

Abstract: In a first aspect, a method of forming an epitaxial film on a substrate is provided. The method includes (a) providing a substrate; (b) exposing the substrate to a silicon source and a carbon source so as to form a carbon-containing silicon epitaxial film; (c) encapsulating the carbon-containing silicon epitaxial film with an encapsulating film; and (d) exposing the substrate to Cl2 so as to etch the encapsulating film. Numerous other aspects are provided.

Abstract: Wafer level arc detection is provided in a plasma reactor using an RF transient sensor coupled to a threshold comparator, and a system controller responsive to the threshold comparator.

Abstract: A method for forming an ultra shallow junction on a substrate is provided. In certain embodiments a method of forming an ultra shallow junction on a substrate is provided. The substrate is placed into a process chamber. A silicon carbon layer is deposited on the substrate. The silicon carbon layer is exposed to a dopant. The substrate is heated to a temperature greater than 950° C. so as to cause substantial annealing of the dopant within the silicon carbon layer. In certain embodiments the substrate is heated to a temperature between about 1000° C. and about 1100°. In certain embodiments the substrate is heated to a temperature between about 1030° C. and 1050° C. In certain embodiments, a structure having an abrupt p-n junction is provided.

Abstract: Methods for implanting ions into a substrate by a plasma immersion ion implanting process are provided. In one embodiment, the method for implanting ions into a substrate by a plasma immersion ion implantation process includes providing a substrate into a processing chamber, supplying a gas mixture including a reacting gas and a reducing gas into the chamber, and implanting ions from the gas mixture into the substrate. In another embodiment, the method includes providing a substrate into a processing chamber, supplying a gas mixture including reacting gas and a hydrogen containing reducing gas into the chamber, and implanting ions from the gas mixture into the substrate.

Abstract: Photovoltaic devices and methods of manufacture are provided. In an embodiment, the devices comprise a micro-crystal silicon cell having an amorphous silicon layer formed on the micro-crystal cell.

Abstract: Embodiments of the present invention pertain to methods of forming patterned features on a substrate having a reduced pitch in two dimensions as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask. A spacer layer is formed over a two-dimensional square grid of cores with a thickness chosen to leave a dimple at the center of four cores on the corners of a square. The spacer layer is etched back to reveal the substrate at the centers of the square. Removing the core material results in double the pattern density of the lithographically defined grid of cores. The regions of exposed substrate may be filled again with core material and the process repeated to quadruple the pattern density.

Abstract: Embodiments of the present invention pertain to methods of forming features on a substrate using a self-aligned double patterning (SADP) process. A conformal layer of non-sacrificial material is formed over features of sacrificial structural material patterned near the optical resolution of a photolithography system using a high-resolution photomask. An anisotropic etch of the non-sacrificial layer leaves non-sacrificial ribs above a substrate. A gapfill layer deposited thereon may be etched or polished back to form alternating fill and non-sacrificial features. No hard mask is needed to form the non-sacrificial ribs, reducing the number of processing steps involved.

Abstract: Methods and apparatus for rapid thermal processing of a planar substrate including axially aligning the substrate with a substrate support or with an empirically determined position are described. The methods and apparatus include a sensor system that determines the relative orientations of the substrate and the substrate support.

Abstract: A system. method and apparatus to monitor a frictional coefficient of a substrate undergoing polishing is described. A polishing pad assembly includes a polishing layer including a polishing surface, and a substrate contacting member flexibly coupled to the polishing layer having a top surface to contact an exposed surface of a substrate. At least a portion of the top surface is substantially coplanar with the polishing surface. A sensor is provided to measure a lateral displacement of the substrate contacting member. Some embodiments may provide accurate endpoint detection during chemical mechanical polishing to indicate the exposure of an underlying layer.

Abstract: A method of processing a workpiece in the chamber of a plasma reactor includes introducing a process gas into the chamber, simultaneously (a) capacitively coupling VHF plasma source power into a process region of the chamber that overlies the wafer, and (b) inductively coupling RF plasma source power into the process region, and controlling plasma ion density by controlling the effective frequency of the VHF source power. In a preferred embodiment, the step of coupling VHF source power is performed by coupling VHF source power from different generators having different VHF frequencies, and the step of controlling the effective frequency is performed by controlling the ratio of power coupled by the different generators.

Abstract: An apparatus and method for inspecting wafers at a reclaim factory is described. Embodiments of the invention describe an apparatus in which a wafer ID and wafer thickness may be simultaneously measured. A wafer is placed onto a sloped surface and positioned by aligning a notch in the wafer with a pin located on the surface, and by propping the wafer against a pair of laterally opposite restraints. In one embodiment, a foot-switch is used to trigger the simultaneous wafer ID and wafer thickness measurements.

Abstract: A method for fabricating a gate dielectric of a field effect transistor is provided. In one embodiment, the method includes removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, forming an oxide layer over the gate dielectric layer, and annealing the layers and underlying thermal oxide/silicon interface. Optionally, the oxide layer may be nitridized prior to forming the gate dielectric layer. In one embodiment, the oxide layer on the substrate is formed by depositing the oxide layer, and the oxide layer on the gate dielectric layer is formed by oxidizing at least a portion of the gate dielectric layer using an oxygen-containing plasma. In another embodiment, the oxide layer on the gate dielectric layer is formed by forming a thermal oxide layer, i.e., depositing the oxide layer on the gate dielectric layer.

Abstract: The invention relates to a coating for temperable substrates, in particular of glass panes. This coating comprises for example directly on the substrate an Si3N4 layer, thereon a CrN layer, thereon a TiO2 layer and lastly an Si3N4 layer.

Abstract: A method and apparatus for plating a metal onto a substrate. One embodiment of the invention provides an apparatus for electrochemically plating a substrate. The apparatus comprises a fluid basin configured to retain a plating solution therein, an anode assembly disposed in the fluid basin, a substrate support member configured to support the substrate and contact the substrate electrically, and an encased auxiliary electrode assembly disposed in the fluid basin. The encased auxiliary electrode assembly generally comprises an auxiliary electrode disposed in a protective tube.

Abstract: A carrier head that has a base assembly, a retaining ring assembly, a carrier ring, and a flexible membrane is described. The flexible membrane has a main portion and an outer annular portion, wherein a junction between the main portion and the outer annular portion comprises a peripheral edge hinge and an annular recess above the hinge along the outer wall of the outer annular portion.

Abstract: Semi-transparent thin-film photovoltaic modules and methods of making the same are described. A thin-film photovoltaic module comprises a transparent conductive oxide layer, a photoabsorptive layer and a reflective back contact layer. A series of scribes is created between application of each layer with some scribes rendering transparent portions of the final module.