Abstract: The present disclosure is generally related to 3D imaging capable OLED displays. A light field display comprises an array of 3D light field pixels, each of which comprises an array of corrugated OLED pixels, a metasurface layer disposed adjacent to the array of 3D light field pixels, and a plurality of median layers disposed between the metasurface layer and the corrugated OLED pixels. Each of the corrugated OLED pixels comprises primary or non-primary color subpixels, and produces a different view of an image through the median layers to the metasurface to form a 3D image. The corrugated OLED pixels combined with a cavity effect reduce a divergence of emitted light to enable effective beam direction manipulation by the metasurface. The metasurface having a higher refractive index and a smaller filling factor enables the deflection and direction of the emitted light from the corrugated OLED pixels to be well controlled.

Abstract: A piezoelectric device comprises: a substrate (12) and a lead magnesium niobate-lead titanate (PMNPT) piezoelectric film on the substrate (12). The PMNPT film comprises: a thermal oxide layer (20) on the substrate (12); a first electrode above on the thermal oxide layer (20); a seed layer (26) above the first electrode; a lead magnesium niobate-lead titanate (PMNPT) piezoelectric layer (16) on the seed layer (26), and a second electrode on the PMNPT piezoelectric layer (16). The PMNPT film comprises a piezoelectric coefficient (d33) of greater than or equal to 200 pm/V.

Abstract: An apparatus may include a drift tube assembly, comprising a plurality of drift tubes to conduct an ion beam along a beam propagation direction. The plurality of drift tubes may define a multi-gap configuration corresponding to a plurality of acceleration gaps, wherein the plurality of drift tubes further define a plurality of RF quadrupoles, respectively. As such, the plurality of quadrupoles are arranged to defocus the ion beam along a first direction at the plurality of acceleration gaps, respectively, where the first direction extends perpendicularly to the beam propagation direction.

Abstract: Embodiments of the present disclosure relate to a system for pulsed direct-current (DC) biasing and clamping a substrate. In one embodiment, the system includes a plasma chamber having an electrostatic chuck (ESC) for supporting a substrate. An electrode is embedded in the ESC and is electrically coupled to a biasing and clamping network. The biasing and clamping network includes at least a shaped DC pulse voltage source and a clamping network. The clamping network includes a DC source and a diode, and a resistor. The shaped DC pulse voltage source and the clamping network are connected in parallel. The biasing and clamping network automatically maintains a substantially constant clamping voltage, which is a voltage drop across the electrode and the substrate when the substrate is biased with pulsed DC voltage, leading to improved clamping of the substrate.

Abstract: Apparatus and methods to process a substrate comprising a gas distribution assembly comprising a plasma process region with an array of individual plasma sources. A controller is connected to the array of individual plasma sources and the substrate support. The controller is configured monitor the position of the at least one substrate and provide or disable power to the individual plasma sources based on the position of the substrate relative to the individual plasma sources.

Abstract: A processing system may include a plasma chamber operable to generate a plasma, and an extraction assembly, arranged along a side of the plasma chamber. The extraction assembly may include an extraction plate including an extraction aperture, the extraction plate having a non-planar shape, and generating an extracted ion beam at a high angle of incidence with respect to a perpendicular to a plane of a substrate, when the plane of the substrate is arranged parallel to the side of the plasma chamber.

Abstract: Exemplary substrate processing systems may include a chamber body defining a transfer region. The systems may include a first lid plate seated on the chamber body. The first lid plate may define a plurality of apertures through the first lid plate. The systems may include a plurality of lid stacks equal to a number of the plurality of apertures. The systems may define a plurality of isolators. An isolator may be positioned between each lid stack and a corresponding aperture of the plurality of apertures. The systems may include a plurality of annular spacers. An annular spacer of the plurality of annular spacers may be positioned between each isolator and a corresponding lid stack of the plurality of lids stacks. The systems may include a plurality of manifolds. A manifold may be seated within an interior of each annular spacer of the plurality of annular spacers.

Abstract: Embodiments described herein generally relate to apparatuses for processing a substrate. In one or more embodiments, a heater support kit includes a heater assembly contains a heater plate having an upper surface and a lower surface, a chuck ring disposed on at least a portion of the upper surface of the heater plate, a heater arm assembly contains a heater arm and supporting the heater assembly, and a heater support plate disposed between the heater plate and the heater arm and in contact with at least a portion of the lower surface of the heater plate.

Abstract: A substrate oxidation assembly includes: a chamber body defining a processing volume; a substrate support disposed in the processing volume; a plasma source coupled to the processing volume; a steam source fluidly coupled to the processing volume; and a substrate heater. A method of processing a semiconductor substrate includes: initiating conformal radical oxidation of high aspect ratio structures of the substrate comprising: heating the substrate; and exposing the substrate to steam; and conformally oxidizing the substrate. A semiconductor device includes a silicon and nitrogen containing layer; a feature formed in the silicon and nitrogen containing layer having an aspect ratio of at least 40:1; and an oxide layer on the face of the feature having a thickness in a bottom region of the silicon and nitrogen containing layer that is at least 95% of a thickness of the oxide layer in a top region.

Abstract: Implementations described herein generally relate to a method for detecting anomalies in time-series traces received from sensors of manufacturing tools. A server feeds a set of training time-series traces to a neural network configured to derive a model of the training time-series traces that minimizes reconstruction error of the training time-series traces. The server extracts a set of input time-series traces from one or more sensors associated with one or more manufacturing tools configured to produce a silicon substrate. The server feeds the set of input time-series traces to the trained neural network to produce a set of output time series traces reconstructed based on the model. The server calculates a mean square error between a first input time series trace of the set of input time series traces and a corresponding first output time series trace of the set of output time-series traces.

Abstract: Provided here are methods and manufacturing systems to implant protons into SiC IGBT devices at multiple depths in the drift layer of the SiC IGBT device. Provides are SiC IGBT devices manufactured with process steps including multiple proton implant processes where the SiC IGBT device is irradiated with ion to affect proton implantation into the SiC IGBT device at multiple depths in the drift region to reduced minority carrier lifetime.

Abstract: A method and apparatus for calibrating a temperature within a processing chamber are described. The method includes determining an etch rate of a layer within the processing chamber. The processing chamber is a deposition chamber configured for use during semiconductor manufacturing. The etch rate is utilized to determine a temperature within the processing chamber. The temperature within the processing chamber is then subsequently compared to a calibrated temperature to determine a temperature offset. The etch rate is determined using any one of a pyrometer, a reflectometer, a camera, or a mass sensor.

Abstract: A thermal processing apparatus and method in which a first laser source, for example, a CO2 emitting at 10.6 ?m is focused onto a silicon wafer as a line beam and a second laser source, for example, a GaAs laser bar emitting at 808 nm is focused onto the wafer as a larger beam surrounding the line beam. The two beams are scanned in synchronism in the direction of the narrow dimension of the line beam to create a narrow heating pulse from the line beam when activated by the larger beam. The energy of GaAs radiation is greater than the silicon bandgap energy and creates free carriers. The energy of the CO2 radiation is less than the silicon bandgap energy so silicon is otherwise transparent to it, but the long wavelength radiation is absorbed by the free carriers.

Abstract: One or more embodiments described herein relate to selective methods for fabricating devices and structures. In these embodiments, the devices are exposed inside the process volume of a process chamber. Precursor gases are flowed in the process volume at certain flow ratios and at certain process conditions. The process conditions described herein result in selective epitaxial layer growth on the {100} planes of the crystal planes of the devices, which corresponds to the top of each of the fins. Additionally, the process conditions result in selective etching of the {110} plane of the crystal planes, which corresponds to the sidewalls of each of the fins. As such, the methods described herein provide a way to grow or etch epitaxial films at different crystal planes. Furthermore, the methods described herein allow for simultaneous epitaxial film growth and etch to occur on the different crystal planes.

Abstract: Exemplary substrate processing systems may include a transfer region housing defining an internal volume. A sidewall of the transfer region housing may define a sealable access for providing and receiving substrates. The systems may include a plurality of substrate supports disposed within the transfer region. The systems may also include a transfer apparatus having a central hub including a first shaft and a second shaft concentric with and counter-rotatable to the first shaft. The transfer apparatus may include a first end effector coupled with the first shaft. The first end effector may include a plurality of first arms. The transfer apparatus may also include a second end effector coupled with the second shaft. The second end effector may include a plurality of second arms having a number of second arms equal to the number of first arms of the first end effector.

Abstract: Apparatus and methods for improving film uniformity in a physical vapor deposition (PVD) process are provided herein. In some embodiments, a PVD chamber includes a pedestal disposed within a processing region of the PVD chamber, the pedestal having an upper surface configured to support a substrate thereon, a first motor coupled to the pedestal, a lid assembly comprising a first target, a first magnetron disposed over a portion of the first target, and in a region of the lid assembly that is maintained at atmospheric pressure, a first actuator configured to translate the first magnetron in a first direction, a second actuator configured to translate the first magnetron in a second direction, and a system controller that is configured to cause the first magnetron to translate along at least a portion of a first path by causing the first actuator and second actuator to simultaneously translate the first magnetron.

Abstract: Memory cells in a memory array may be configured to include a fuse that will blow in the case of a defective cell. In a 1T-1R memory cell, a fuse may be placed in series with the select element and/or the memory element to counteract a short-circuit in either of these elements. A fuse may be formed by selectively etching a phase-change material (PCM) between two electrodes to leave a cavity. When sufficient energy is applied to the PCM material, the PCM filament will break its crystalline structure and be distributed within the cavity. This prevents the PCM material from recrystallizing. Another fuse may be formed by depositing a material between two electrodes that is doped with mobile ions. When subjected to an excessive signal, the resulting electric field may push these ions permanently towards one of the electrodes, thereby permanently destroying the conductive pathway.

Abstract: Embodiments of multi-zone showerheads are provided herein. In some embodiments, a multi-zone showerhead includes: a body having an outer surface and including a plurality of fluidly independent plenums; and a plurality of gas distribution plugs extending through the body, wherein at least one gas distribution plug includes a first internal gas passageway coupling a first plenum of the plurality of fluidly independent plenums to the outer surface and a second internal gas passageway coupling a second plenum of the plurality of fluidly independent plenums to the outer surface. In some embodiments, the body can include: a top plate; a bottom plate; and one or more intermediate plates disposed between the top plate and the bottom plate, wherein individual plenums of the plurality of fluidly independent plenums are respectively defined between adjacent plates of the top plate, the bottom plate, and the one or more intermediate plates.

Abstract: Processing methods for forming iridium-containing films at low temperatures are described. The methods comprise exposing a substrate to iridium hexafluoride and a reactant to form iridium metal or iridium silicide films. Methods for enhancing selectivity and tuning the silicon content of some films are also described.

Abstract: Embodiments disclosed herein include a semiconductor manufacturing tool with a hybrid model and methods of using the hybrid model for processing wafers and/or developing process recipes. In an embodiment, a method for developing a semiconductor manufacturing process recipe comprises selecting one or more device outcomes, and querying a hybrid model to obtain a process recipe recommendation suitable for obtaining the device outcomes. In an embodiment, the hybrid process model comprises a statistical model and a physical model. In an embodiment, the method may further comprise executing a design of experiment (DoE) on a set of wafers to validate the process recipe recommended by the hybrid process model.