Abstract: A substrate oxidation assembly includes: a chamber body defining a processing volume; a substrate support disposed in the processing volume; a plasma source coupled to the processing volume; a steam source fluidly coupled to the processing volume; and a substrate heater. A method of processing a semiconductor substrate includes: initiating conformal radical oxidation of high aspect ratio structures of the substrate comprising: heating the substrate; and exposing the substrate to steam; and conformally oxidizing the substrate. A semiconductor device includes a silicon and nitrogen containing layer; a feature formed in the silicon and nitrogen containing layer having an aspect ratio of at least 40:1; and an oxide layer on the face of the feature having a thickness in a bottom region of the silicon and nitrogen containing layer that is at least 95% of a thickness of the oxide layer in a top region.

Abstract: Embodiments described herein generally relate to apparatuses for processing a substrate. In one or more embodiments, a heater support kit includes a heater assembly contains a heater plate having an upper surface and a lower surface, a chuck ring disposed on at least a portion of the upper surface of the heater plate, a heater arm assembly contains a heater arm and supporting the heater assembly, and a heater support plate disposed between the heater plate and the heater arm and in contact with at least a portion of the lower surface of the heater plate.

Abstract: Exemplary substrate processing systems may include a transfer region housing defining an internal volume. A sidewall of the transfer region housing may define a sealable access for providing and receiving substrates. The systems may include a plurality of substrate supports disposed within the transfer region. The systems may also include a transfer apparatus having a central hub including a first shaft and a second shaft concentric with and counter-rotatable to the first shaft. The transfer apparatus may include a first end effector coupled with the first shaft. The first end effector may include a plurality of first arms. The transfer apparatus may also include a second end effector coupled with the second shaft. The second end effector may include a plurality of second arms having a number of second arms equal to the number of first arms of the first end effector.

Abstract: Methods and systems are described for generating assessment maps. A method includes receiving a first vector map comprising a first set of vectors each indicating a distortion of a particular location on a substrate and generating a second vector map indicating a change in direction of a magnitude of the distortion of the particular location on the substrate. The method further includes generating a third vector map comprising vectors reflecting reduced noise in distortions across the plurality of locations on the substrate and generating a fourth vector map projecting a direction component of each vector component in the third set of vectors to a radial direction. The method further includes generating a fifth vector map by grouping the vectors of the fourth set of vectors and determining a magnitude associated with each group of vectors.

Abstract: Apparatus and methods to process a substrate comprising a gas distribution assembly comprising a plasma process region with an array of individual plasma sources. A controller is connected to the array of individual plasma sources and the substrate support. The controller is configured monitor the position of the at least one substrate and provide or disable power to the individual plasma sources based on the position of the substrate relative to the individual plasma sources.

Abstract: Apparatuses and methods to provide electronic devices having metal films are provided. Some embodiments of the disclosure utilize a metallic tungsten layer as a liner that is filled with a metal film comprising cobalt. The metallic tungsten layer has good adhesion to the cobalt leading to enhanced cobalt gap-fill performance.

Abstract: Memory cells in a memory array may be configured to include a fuse that will blow in the case of a defective cell. In a 1T-1R memory cell, a fuse may be placed in series with the select element and/or the memory element to counteract a short-circuit in either of these elements. A fuse may be formed by selectively etching a phase-change material (PCM) between two electrodes to leave a cavity. When sufficient energy is applied to the PCM material, the PCM filament will break its crystalline structure and be distributed within the cavity. This prevents the PCM material from recrystallizing. Another fuse may be formed by depositing a material between two electrodes that is doped with mobile ions. When subjected to an excessive signal, the resulting electric field may push these ions permanently towards one of the electrodes, thereby permanently destroying the conductive pathway.

Abstract: The present disclosure generally relates to a pin-less substrate transfer apparatus and method for a processing chamber. The processing chamber includes a pedestal. The pedestal includes a pedestal plate. The pedestal plate has a radius, a top surface, and a bottom surface. The pedestal plate further includes a plurality of cut outs on a perimeter of the pedestal plate. Flat edges are disposed on opposite sides of the pedestal plate. Recesses are disposed in the bottom surface below each of the flat edges.

Abstract: Provided here are methods and manufacturing systems to implant protons into SiC IGBT devices at multiple depths in the drift layer of the SiC IGBT device. Provides are SiC IGBT devices manufactured with process steps including multiple proton implant processes where the SiC IGBT device is irradiated with ion to affect proton implantation into the SiC IGBT device at multiple depths in the drift region to reduced minority carrier lifetime.

Abstract: Process assemblies and cable management assemblies for managing cables in tight envelopes. A processing assembly includes a top chamber having at least one substrate support, a support shaft, a robot spindle assembly, a stator and a cable management system. The cable management system includes an inner trough assembly and an outer trough assembly configured to move relative to one another, and a plurality of chain links configured to house at least one cable for delivering power to the process assembly.

Abstract: A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.

Abstract: Methods and apparatus for creating a dual metal interconnect on a substrate. In some embodiments, a first liner of a first nitride material is deposited into at least one 1X feature and at least one wider than 1X feature, the first liner has a thickness of less than or equal to approximately 12 angstroms; a second liner of a first metal material is deposited into the at least one 1X feature and at least one wider than 1X feature; the first metal material is reflowed such that the at least one 1X feature is filled with the first metal material and the at least one wider than 1X feature remains unfilled with the first metal material; a second metal material is deposited on the first metal material, and the second metal material is reflowed such that the at least one wider than 1X feature is filled with the second metal material.

Abstract: Embodiments of the present disclosure relate to a system for pulsed direct-current (DC) biasing and clamping a substrate. In one embodiment, the system includes a plasma chamber having an electrostatic chuck (ESC) for supporting a substrate. An electrode is embedded in the ESC and is electrically coupled to a biasing and clamping network. The biasing and clamping network includes at least a shaped DC pulse voltage source and a clamping network. The clamping network includes a DC source and a diode, and a resistor. The shaped DC pulse voltage source and the clamping network are connected in parallel. The biasing and clamping network automatically maintains a substantially constant clamping voltage, which is a voltage drop across the electrode and the substrate when the substrate is biased with pulsed DC voltage, leading to improved clamping of the substrate.

Abstract: Embodiments of the disclosure are directed to methods of depositing a molybdenum film directly on a substrate surface (e.g., a low-K dielectric material) by exposing the substrate surface to a molybdenum-containing precursor and a plasma at a temperature of less than or equal to 400° C. The molybdenum-containing precursor comprises one or more of molybdenum pentachloride (MoCl5), molybdenum dioxide dichloride (MoO2Cl2), molybdenum oxytetrachloride (MoOCl4), molybdenum hexacarbonyl, bis(tert-butylimido)-bis(dimethylamido)molybdenum, or bis(ethylbenzene) molybdenum. The plasma comprises one or more of hydrogen (H2), nitrogen (N2), or a silane (SixHy). In some embodiments, when the molybdenum-containing precursor comprises molybdenum hexafluoride (MoF6), the plasma does not include hydrogen (H2).

Abstract: Embodiments of the present technology relate to semiconductor processing methods that include providing a structured semiconductor substrate including a trench having a bottom surface and top surfaces. The methods further include depositing a portion of a silicon-containing material on the bottom surface of the trench for at least one deposition cycle, where each deposition cycle includes: depositing the portion of the silicon-containing material on the bottom surface and top surfaces of the trench, depositing a carbon-containing mask layer on the silicon-containing material on the bottom surface of the trench, where the carbon-containing mask layer is not formed on the top surfaces of the trench, removing the portion of the silicon-containing material from the top surfaces of the trench, and removing the carbon-containing mask layer from the silicon-containing material on the bottom surface of the trench, where the as-deposited silicon-containing material remains on the bottom surface of the trench.

Abstract: Methods and apparatus for processing a substrate include cleaning and self-assembly monolayer (SAM) formation for subsequent reverse selective atomic layer deposition. An apparatus may include a process chamber with a processing volume and a substrate support including a pedestal, a remote plasma source fluidly coupled to the process chamber and configured to produce radicals or ionized gas mixture with radicals that flow into the processing volume to remove residue or oxides from a surface of the substrate, a first gas delivery system with a first ampoule configured to provide at least one first chemical into the processing volume to produce a SAM on the surface of the substrate, a heating system located in the pedestal and configured to heat a substrate by flowing gas on a backside of the substrate, and a vacuum system fluidly coupled to the process chamber and configured to control heating of the substrate.

Abstract: Exemplary deposition methods may include delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the silicon-containing precursor and the boron-containing precursor. A flow rate ratio of the hydrogen-containing precursor to either of the silicon-containing precursor or the boron-containing precursor is greater than or about 1:1. The methods may include forming a plasma of all precursors within the processing region of a semiconductor processing chamber. The methods may include depositing a silicon-and-boron material on a substrate disposed within the processing region of the semiconductor processing chamber.

Abstract: A method of fabricating a multi-color display includes dispensing a photo-curable fluid over a display having an array of light emitting diodes (micro-LEDs) disposed below a cover layer. The cover has an outer surface with a plurality of recesses, and the photo-curable fluid fills the recesses. The photo-curable fluid includes a color conversion agent. A plurality of LEDs in the array are activated to illuminate and cure the photo-curable fluid to form a color conversion layer in the recesses over the activated LEDs. This layer will convert light from these LEDs to light of a first color. An uncured remainder of the photo-curable fluid is removed. Then the process is repeated with a different photo-curable fluid having a different color conversion agent and a different plurality of LEDs. This forms a second color conversion layer in different plurality of recesses to convert light from these LEDs to light of a second color.

Abstract: Provided herein are apparatus, systems and methods for processing reticle blanks. A reticle processing system includes a support assembly having a plate coupled to a frame, and a carrier base assembly supported on the support assembly. The carrier base assembly comprises a wall extending from a top surface of the carrier base and defining a containment region for a reticle.

Abstract: Embodiments of fast gas exchange (FGE) manifolds are provided herein. In some embodiments, a FGE manifold includes: a manifold housing having a plurality of inlets and a plurality of outlets for flowing a plurality of process gases therethrough, wherein the plurality of outlets correspond with a plurality of zones in the process chamber; a plurality of hybrid valves disposed in the manifold housing and fluidly coupled to the plurality of inlets; a plurality of mass flow controllers disposed in the manifold housing downstream of the plurality of hybrid valves; a plurality of mixing lines extending downstream from the plurality of mass flow controllers to a plurality of outlet lines; and a plurality of outlet valves disposed in line with corresponding ones of the plurality of outlet lines, wherein a flow path is defined between each inlet of the plurality of inlets and each outlet of the plurality of outlets.