Abstract: A system for controlling initialization and self test operations in a multiprocessor system facilitates the use of central processing units based around differing microprocessor types. More specifically, the present invention involves storing configuration information, initialization self-test code, and boot code specific to each processor, memory module, or I/O circuit board in non-executable form in a non-volatile memory, on the respective circuit board, and storing the executable portion of the boot code needed by the initial boot processor in a centrally accessible non-volatile memory.

Abstract: A multiprocessor computer system includes specially designed snoop circuitry to prevent data loss during write-back cycles. A memory controller within a main memory module determines if a data request at a specified address corresponds to a cacheable memory address. If it is determined that the requested data is located at a cacheable memory address, then the memory controller initiates a snoop cycle. When a snoop cycle is initiated, a write-back buffer within the main memory module is first examined to determine if data contained within the write-back buffer is the requested data, so that the data within the write-back buffer has an associated address which is the designated cacheable memory address. If the write-back buffer does not contain the requested data, then the memory controller causes the cache memories associated with the multiple processors within the multiprocessor system to be examined.

Abstract: A system tracks the amount of time a computer system has operated, after its delivery to a new user. The system includes a terminate and stay resident (TSR) program which is loaded each time the computer is booted. The program counts system timer ticks and, at predetermined intervals but only when the operating system is idle, logs the amount of time counted in a log file located on the computer's local hard drive.

Abstract: An improved computer chassis having a backplane with ground pads thereon for contacting fingers formed in channels in the chassis. The backplane is secured in the chassis without the use of screws. The fingers are defined within channels formed by a structure at the rear of a disk drive cage. The computer system further includes a plurality of disk drives mounted on trays which have rear pins that engage guide apertures formed in the backplane. The backplane is inserted within the channels and held therein by a pair of levers on outer corners which engage with catch members on the computer chassis. The engagement between the levers and the catch members ensures the backplane will remain in position during assembly and shipping. The backplane includes ground pads connected to a ground plane within the backplane. The ground pads engage the fingers on the channels to provide a secure electrical interconnection between the chassis and the backplane.

Abstract: A system for use in a computer having a display for automatically configuring graphical user interface ("GUI") display panels comprising buttons for representing groups, or suites, of related items in a visually attractive manner. In a preferred embodiment, a panel creation engine processes a series of script files to determine, for each group of related items to be displayed as a single suite, an appropriate background template or preprocessed background bitmap and an appropriate button template to be used in representing the suite on the display, based on desired color depth. In particular, the panel creation engine processes a panel location script ("PLS") file to locate, for each suite, a panel configuration script ("PCS") file associated with the suite.

Abstract: A method for toggling the output pins of a IC chip to satisfy an ASIC manufacturer's output toggle test requirements parallel loads data from an IC tester into the IC's JTAG boundary scan data shift register, so that the parallel loaded data is an alternating high and low data bits. The test pattern of alternating data bits is then latched to the JTAG data latch register and driven onto the output pins of the IC chip. The bidirectional buffers connected to the output pins are then enabled for output while the IC tester tri-states its alternating data test pattern. The test pattern is then shifted by one bit within the IC's JTAG shift register and parallel loaded into the JTAG latch register on the next clock cycle. In this manner, the complement of a test pattern driven onto the output pins by the external test circuit is driven out from the IC chip.

Abstract: A memory mapped keyboard controller within a peripheral controller for use in an Industry Standard Architecture (ISA) computer provides a method and apparatus for efficiently monitoring and reading a keyboard switch matrix. In a first mode of operation, the controller activates all the columns and monitors all the rows in the switch matrix to detect when any one or more of the rows becomes active, indicating that at least one key on the keyboard has been pressed. When any row in the matrix is detected as active, then the keyboard controller enters a second mode wherein it selectively activates individual columns and monitors the rows in the switch matrix to detect which row and column contain the activated switch. When the switch location is determined, this location is interpreted by the keyboard controller into a scan code for the ISA computer.

Abstract: A state machine bus controller for interfacing the CPU of a micro-computer based system with memory and I/O device is described. The controller, while capable of interfacing with a bus which is synchronous in nature, can maintain synchronous handshake with more than one type of microprocessor while providing function and timing parameters to satisfy requirements of an asynchronous bus and more than one type of device which reside on the bus.

Abstract: A power supply for a rechargeable battery in a portable computer system is disclosed which adjusts the level of charging current depending upon the current drawn by the portable computer system. The power supply includes an AC adapter which supplies input current for operating the computer system and for charging the battery. Sensors are connected to the AC adapter, the battery, and an output of the power supply to detect the level of input current from the AC adapter, the level of charging current supplied to the battery, and the output voltage level of the power supply. A controller is connected to each of the sensors and monitors the input current level, the charging current level, and the output voltage level. The controller generates a control signal which indicates whether any one of the levels has exceeded a respective predetermined maximum value.

Abstract: A flexible circuit connector is formed from a flexible printed circuit comprising a plurality of embedded electrically conductive lines partially exposed at a first end of the flexible printed circuit by bending or folding the flexible printed circuit to enable said first end to mate with a board mounted connector, thereby eliminating the need for a mating connector. When the flexible circuit connector is properly inserted into the board mounted connector, the mating of said plurality of exposed electrically conductive lines of said flexible circuit connector with a plurality of metal contacts on the board mounted connector provides an electrical interface between the flexible printed circuit and the board mounted circuit, as well as the boards on which the flexible printed circuit and board mounted connector are attached.

Abstract: A method and apparatus provide a direct memory access (DMA) system that transfers data between a memory in a computer system and a plurality of I/O devices. The DMA system includes at least two channels which operate independently and in an interleaved manner so that multiple DMA transfers can occur concurrently. Each channel includes a pair of buffers so that data can be transferred between one buffer and memory at a rate determined by the memory and data can be transferred between the other buffer and the I/O device at a rate determined by the I/O device. Transfers between the two buffers occur at a data rate determined by the bus connecting the two buffers. Thus, the transfers between the two buffers occur in bursts to optimize the transfer and to reduce the amount of time that the bus is needed for the transfer. Therefore, the bus is available for transfers by the other DMA channel and by other devices on the bus.

Abstract: A suspend (sleep) switch for a portable electronic device, such as a notebook computer, is mounted on a printed circuit board. The suspend switch includes a first contact which is positioned in juxtaposed relationship with a second contact. The contacts are formed from an electrically conductive metal or other electrically conductive material which is sufficiently resilient to support an actuator and to hold the two contacts apart in normal operation. In addition, the resiliency of the two contacts allows the two contacts to adjust to different distances between the printed circuit boards on which the contacts are mounted and the cover of the electronic device which constrains the actuator. When the cover of the electronic device is closed, the actuator pushes the two contacts into electrical contact, preferably with a wiping motion, to provide an electrical connection which can be sensed by circuitry on the printed circuit board.

Abstract: A notebook computer or other electronic device has a flexible cable interconnecting electronic circuitry in a base with electronic circuitry in a cover. A flexible potentiometer is coupled to said flexible cable in a location which bends when said cover is opened and closed with respect to the base. The resistance of the flexible potentiometer has a first value when the cover is closed and has a second value when the cover is open. A detection circuit is responsive to the resistance of the flexible potentiometer and generates an output signal which indicates whether the cover is open or closed.

Abstract: A data ordering system for use with personal computers having data pipelining capability is disclosed. The personal computer comprises a central processing unit (CPU) which issues data requests to one or more data exchange units, such as memory units or data Input/Output units. The data ordering system comprises a finite state machine (FSM) which receives inputs indicative of data requests transmitted by a central processing unit (CPU). The inputs cause the FSM to assume different output states which are indicative of the proper order of data requests. The state outputs of the FSM are used to enable or disable the transmission of data between the data exchange units and the CPU in order to insure the proper order of data responses to the issued data requests.

Abstract: A rotatable and slidable heat pipe apparatus for transferring heat away from a microprocessor chip more rapidly than by heat sink surface area dissipation to the surrounding air alone, comprising a heat sink with an integral cylindrical passageway adapted to receive a first end of a heat pipe shaped like a crankshaft, and a heat spreader formed from a metal plate with a first end rolled up to define a cylindrical opening adapted to receive a second end of the heat pipe. The heat spreader is attached to an underside of a keyboard. Since the heat pipe is able to rotate within the cylindrical passageway and the cylindrical opening, the keyboard can be raised to an open position and lowered to a closed position quickly and simply without the risk of breaking or bending the heat pipe, and manufacturing position tolerances between the heat pipe apparatus components are increased resulting in a simplified manufacturing process.

Abstract: A circuit card retainer for securing a circuit card within a circuit card receiving channel to mitigate the possibility of a circuit card connector jarring loose from a motherboard slot during transit or other vibration or shock causing activity. The circuit card retainer securely retains an inner edge of the circuit card upon insertion of the circuit card, and allows the circuit card to be extracted only if the groove abutment is flexed away from the inner edge of the circuit card, thereby removing the obstruction caused by the groove abutment.

Abstract: A distributed direct memory access (DMA) system includes specially configured hardware connections between at least one slave DMA controller and a central, or master, DMA controller. The specially configured hardware connections allow the slave DMA controllers to request channel configuration information from the central DMA controller when peripheral devices under the control of the slave DMA controllers make a DMA request. After the channel information is transferred from the master DMA controller to the slave DMA controller, the slave DMA controller is able to process DMA requests for the peripheral devices under its control. In one particular embodiment, the master DMA controller is located in a notebook computer and the slave DMA controller is located in a docking station. The master DMA controller and slave DMA controller communicate when the notebook computer is engaged with the docking station.

Abstract: A multiprocessor information processing system has a system bus with interleaved memory modules in communication with multiple CPUs. The multiprocessor system includes a subsystem monitoring circuit which monitors the addresses requested by the local CPU. If the local CPU addresses a memory module which is different from the last accessed memory module, then the subsystem monitoring circuit initiates a request to maintain control of the system bus. In this manner, sequential write and read operations are typically made to interleaved memory modules so that the effects of module recovery time are minimized. The subsystem monitoring circuit includes a transfer count register which indicates how many data transfer cycles can be run in succession before the local CPU has to relinquish control of the system bus. In this manner, fair arbitration is assured for other CPUs contending for control of the system bus.

Abstract: A system for inhibiting interrupts during posted write transfers in a computer system utilizes a buffer to store incoming data and addresses while monitoring incoming addresses to determine if the address is an Input/Output reference to an interrupt controller. If an Input/Output reference to an interrupt controller is detected, a counter is incremented which outputs a logical zero output. A signal indicating a counter value of zero is provided as an input to an AND gate. A second input to the AND gate is provided from an interrupt controller. When the counter contains a non-zero value, a zero input is provided to the AND gate and a zero output is provided to the system bus, regardless of the output from the interrupt controller, inhibiting all further interrupts. Thus, when an interrupt mask is set by a CPU, the present invention immediately inhibits further interrupts from occurring, thereby permitting processing to continue without interruption. As a result, processing time is increased.

Abstract: A rotatable bushing for reducing bending fatigue on a flat cable between a display screen cover and a base of a portable computer comprises an elongate cylindrical body having a diametric slot therethrough. The bushing is positioned along the hinge axis between the cover and the base of the portable computer. The cable extends from the cover display screen, through the slot, and to circuitry within the base of the computer. MYLAR Plastic shields also extend through the slot on either side of the cable. When the cover is closed and opened over 180.degree., the cable applies force to the bushing, which is free to rotate as dictated by the force applied by the cable. The rotation of the bushing effectively provides two bending regions on the top and bottom of the bushing slot so that the cable does not bend through the entire range of motion of the cover at a single point. Since the bending of the cable is distributed, fatigue due to bending stress is significantly decreased.