Abstract: An apparatus and method for processing pixel depth information eliminates stalling of data in a pixel pipeline, by performing late Z processing for one or more pixels currently in the pixel pipeline and early Z processing for one or more pixels entering the pixel pipeline. The apparatus and method also includes determining whether the late Z processing for the one or more pixels currently in the pixel pipeline has been completed. The apparatus and method also includes solely performing early Z processing for subsequent pixels entering the pixel pipeline responsive to determining that late Z processing for the one or more pixels currently in the pixel pipeline has been completed. The methods and apparatus, facilitates concurrent processing of early and late Z data to avoid flushing portions of the pixel pipeline.

Abstract: The embodiments of the present invention are a method and apparatus to perform anti-aliasing using multi-sampling on a non-power-of-two pixel grid. Using the present invention with 6 sample multisampling gives the same visual antialiasing quality as 8 samples using a prior art technique but uses less memory. A non-power-of-two equally spaced sample from a conventional grid of size N×N, where N is 12 can be chosen using the present invention. A scan conversion to determine the set of pixels covered by a polygon is performed in two parts. According to one embodiment, the present invention can multiply and divide by “N” in order to multisample an image using samples per pixel chosen from a N×N sub-sample grid, where “N” is not necessarily a power of 2. The present invention performs the divide by “N” step, where the step is achieved using a quick divide by 3 or 12 technique.

Abstract: A method and apparatus for nested control flow includes a processor having at least one context bit. The processor includes a plurality of arithmetic logic units for performing single instruction multiple data (SIMD) operations. The method and apparatus further includes a first memory device storing a plurality of instructions wherein each of the plurality of instructions includes a plurality of extra bits. The processor is operative to execute the instructions based on the extra bits and in conjunction with a context bit. The method and apparatus further includes a second memory device, such as a general purpose register operably coupled to the processor, the second memory device receiving an incrementing counter instruction upon the execution of one of the plurality of instructions. As such, the method and apparatus allows for nested control flow through a single context bit in conjunction with instructions having a plurality of extra bits.

Abstract: In a robotic tool coupler, a rotating cam member having a plurality of surfaces formed therein urges a plurality of ball members in one tool coupling unit radially to contact an angled surface in the other tool coupling unit. Further rotation of the cam member exerts a radial force through the ball members onto the angled surface. A component of that force is directed by the angled surface toward the opposite tool coupling unit, locking the two units together. The cam member may include a failsafe surface and/or a failsafe lobe to maintain the two units locked together in the event of a loss of power to positively actuate the cam member.

Abstract: An error detection apparatus and method compares a first hardwired value such as a first clock threshold, and a second hardwired value such as a second clock threshold, and generates an indication that there is an error in a clock signal based on a comparison of the first hardwired value and the second hardwired value to the clock signal. If an error is detected, the error detection apparatus will, for example, interrupt clock recovery logic to take proper action for recovery of a clock generation circuit that generated the clock signal. The clock signal may be generated based on, for example, a reference clock signal that may be provided by an external source clock, or any other suitable source.

Abstract: A robotic tool changer comprises first and second units, operative to be separately attached to a robot and a robotic tool, and further operative to be selectively coupled together and decoupled. The first and second units are coupled and decoupled by an electric motor. Power from the electric motor may be applied to couple and decouple the first and second units in a variety of ways.

Abstract: A method and apparatus for rate control for a constant-bit-rate finite-buffer-size video encoder is described. Rate control is provided by adjusting the size of non-intra frames based on the size of intra frames. A sliding window approach is implemented to avoid excessive adjustment of non-intra frames located near the end of a group of pictures. A measurement of “power” based on a sum of absolute values of pixel values is used. The “power” measurement is used to adjust a global complexity value, which is used to adjust the sizes of frames. The global complexity value responds to scene changes. An embodiment of the invention calculates and uses L1 distances and pixel block complexities to provide rate control. An embodiment of the invention implements a number of bit predictor block. Predictions may be performed at a group-of-pictures level, at a picture level, and at a pixel block level. An embodiment of the invention resets a global complexity parameter when a scene change occurs.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: To provide reduced power consumption of a co-processor, a low power dedicated memory is provided. During a low power state, a processing component of the co-processor is instructed to use the low power dedicated memory and a first memory device, normally used by the processing component, is thereafter operated in a reduced power mode for the duration of the low power state. Preferably, the low power dedicated memory has a storage capacity that is significantly less than the storage capacity of the first memory. When an operating state other than the low power state is detected, normal power consumption by the first memory is resumed and the co-processor is directed to use the first memory once again. In this manner, the present invention allows co-processors, and preferably graphics co-processors, to operate in a beneficial low power mode thereby reducing power consumption.

Abstract: A technique for processing at least one bad pixel occurring in an image sensing system is provided. Dynamic bad pixel detection is performed on a plurality of streaming pixels taking from at least one controlled image and value and coordinate information for each bad pixel is subsequently stored as stored bad pixel information. Thereafter, static bad pixel correction may be performed based on the stored bad pixel information. The stored bad pixel information may be verified based on histogram analysis performed on the plurality of streaming pixels. The technique for processing bad pixels in accordance with the present invention may be embodied in suitable circuitry or, more broadly, within devices incorporating image sensing systems.

Abstract: A graphics processing system comprises a command processing engine capable of processing pixel command threads and vertex command threads. The command processing engine is coupled to both a renderer and a scan converter. Upon completing processing of a command thread, which may comprise a pixel command thread or a vertex command thread, the command engine provides the command thread to either the renderer or the scan converter.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context. Without modifying a pre-existing operating system of the computer, an entry exception is establishing to be raised on each entry to the operating system at a specified entry point or on a specified condition. The entry exception has an associated entry handler programmed to save a context of an interrupted thread and modify the thread context before delivering the modified context to the operating system. A resumption exception is established to be raised on each resumption from the operating system complementary to one of the specified entries. The resumption exception has an associated exit handler programmed to restore the context saved by a corresponding execution of the entry handler.

Abstract: A device and method for controlling generation of a final pixel utilizes a conditional statement, referred to as an IF_NEIGHBOR statement, which when compiled, causes a programmable pixel shader to perform mip map texture lookups even if a pixel of interest does not meet the condition of the conditional statement. As such, any neighboring pixels needed for mip map selection have their associated shader code guaranteed to execute even though the pixel of interest may fail the conditional portion of the conditional statement. The device and method executes texture address calculations for pixels within a region and for pixels outside of a region but only those necessary to determine the mip map level corresponding to a pixel within the region. Execution of shader code for a current pixel is executed if any of the surrounding neighboring pixels meet the desired condition even if the current pixel does not meet the condition.

Abstract: A computer system has a processor and a queue for storing instructions for execution by the processor. The processor is capable of being clocked at a plurality of different clock frequencies. In one embodiment, the clocking frequency is determined by estimating a short or long term load associated with the stored instructions. In another embodiment, the clocking frequency is determined by analyzing a set of the stored instructions.

Abstract: Power consumption in a portable computer device that provides true-color simulation on a liquid crystal display can be realized by selectively operating a graphics controller that drives the LCD to selectively enable or disable true color simulation. Disabling dithering which provides true color simulation in an LCD, can significantly reduce power consumption by a portable computer device.

Abstract: Min-axis based mip map determination logic receives a plurality of texture space derivatives with respect to screen space for a given pixel and texel location and selects from a plurality of mip map levels a mip map level based on a min-axis without using a max-axis value and without using an amount of anisotropy. The plurality of mip map levels corresponds to mip map levels of a mip chain. The min-axis may be identified as the squares of the texture space derivatives with respect to either the x-axis or the y-axis of screen space. Selecting the mip map level based on the min-axis ensures that each texel of the selected mip map never maps to more than one pixel during texture mapping where the main texture is of sufficient resolution. Thus, using the mip map level based on the min-axis to fetch texture data from memory and render images results in few aliasing artifacts.

Abstract: A robotic tool coupling system includes a first connecting unit including a piston movable along a longitudinal axis. The piston includes a multifaceted contact surface comprising a tapered locking surface; an initial actuating surface having an angle with respect to the axis not greater than the angle of the tapered locking surface; and a failsafe surface interposed between the tapered locking surface and the initial actuating surface. The system includes a second connecting unit having a plurality of rolling members disposed in a retention chamber including at least one angled surface operative to lock the first and second units together when the rolling members are forced against the angled surfaces by the tapered locking surface. The piston contact surface may additionally include a step surface, generally normal to the longitudinal axis, and a retention surface generally parallel to the axis.

Abstract: A computer binary translator translates at least a segment of a binary representation of a program from a first instruction set architecture to a second instruction set architecture. A sequence of side-effects in the translation differs from a sequence of side-effects in the original. The translation distinguishes memory loads that are believed to be directed to well-behaved memory from memory loads that are believed to be directed to non-well-behaved memory device(s). Instruction execution circuitry identifies a memory reference that has a side-effect that has been reordered by translation, the memory reference having been believed at translation time to be directed to well-behaved memory but at execution it is found that the reference cannot be guaranteed to be well-behaved. The instruction execution circuitry identifies whether the difference in side-effect order may have a material effect on the execution of the program. A roll-back program state is established, and execution of the original code resumes.

Abstract: A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients. A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory.