Abstract: A soil stabilizer treating earth includes a stabilizer frame, a rotor rotatably mounted thereon and including a cutting tool for cutting earth and being movable such that the rotor may engage various depths of earth, a rotatable axle, and a track apparatus mounted on the rotatable axle, the track apparatus supporting the stabilizer frame and providing for movement of the stabilizer frame and rotor across the ground surface. The track apparatus may include a continuous flexible track having an upper length and a ground-engaging lower length and including an inner surface, an axle wheel mountable to the rotatable axle for rotational movement therewith, the axle wheel engaging the inner surface of the flexible track along the upper length to drive the flexible track in response to rotation of the axle, and an apparatus frame for mounting the axle wheel.

Abstract: Embodiments of the present invention relate to nickel-base alloys, and in particular 718-type nickel-base alloys, having a desired microstructure that is predominantly strengthened by ??-phase precipitates and comprises an amount of at least one grain boundary precipitate. Other embodiments of the present invention relate to methods of heat treating nickel-base alloys, and in particular 718-type nickel-base alloys, to develop a desired microstructure that can impart thermally stable mechanical properties. Articles of manufacture using the nickel-base alloys and methods of heat treating nickel-base alloys according to embodiments of the present invention are also disclosed.

Abstract: A cross-coupled, latching voltage level converter to convert a signal from a first voltage domain to a second voltage domain and hold an output logic level is disclosed. The converter includes back-to-back first and second inverter circuits coupled to a first voltage source operable at a first voltage level. A transistor is coupled between an output of the first inverter and ground potential, the first transistor having a gate coupled to an input signal operable at a second voltage level. A second transistor is coupled between the output of the second inverter and ground potential, the second transistor having a gate coupled to an inverse of the input signal operable at the second voltage, wherein a terminal of the second transistor delivers an output signal operable at the first voltage level and corresponding to the same logic state as the input signal.

Abstract: A method for refining and casting metals and metal alloys includes melting and refining a metallic material and then casting the refined molten material by a nucleated casting technique. The refined molten material is provided to the atomizing nozzle of the nucleated casting apparatus through a transfer apparatus adapted to maintain the purity of the molten refined material. An apparatus including a melting and refining apparatus, a transfer apparatus, and a nucleated casting apparatus, in serial fluid communication, also is disclosed.

Abstract: The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output.

Abstract: Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.

Abstract: A method and apparatus for performing tessellation lighting operations for video graphics primitives in a video graphics system is presented. When the vertex parameters corresponding to the vertices of a video graphics primitive are received, a tessellation operation is performed such that a number of component primitives are generated. The vertex parameters corresponding to the vertices of the component primitives are then calculated utilizing the vertex parameters for the original video graphics primitive. Such calculation operations include determining a corresponding normal vector for each component primitive vertex. Each of the component primitives is then individually processed. Such processing may include calculating the lighting effects for each component primitive and performing additional processing operations that generate pixel fragments for the primitive.

Abstract: A computing device that allows for a flexible allocation of bandwidth among peripheral devices using a peripheral bus is disclosed. The computing device includes a peripheral bus and at least two slots. The computing device may be used with a single peripheral card or multiple peripheral cards. In a multi-card configuration the invention allows the bandwidth on the peripheral bus to be shared by all the cards. In a single-card configuration, the computing device allows available bandwidth on the peripheral bus to be used by a single card. The device is particularly useful with PCI express compliant expansion cards, such as graphics adapters.

Abstract: A block-based image compression method and encoder/decoder circuit compress a plurality of pixels in a block where each pixel includes a corresponding color value and a corresponding luminance value. The encoder circuit includes a luminance-level-based representative color generator to generate representative color values for each of a plurality of luminance levels to produce at least a high color value and a low color value. In response to generating the representative color values, the luminance-level-based representative color generator associates each of the pixels in the block with one of the plurality of representative color values to produce corresponding bitmap values. The encoder circuit further includes a color type block generator to perform at least one of: (a) generate block color data indicating a regular/alternate color block type and (b) representing a block color type by ordering the representative color values that are to be sent to a decoder.

Abstract: A pneumatically driven deburring device having a housing and a pneumatic motor mounted therein which is adapted to receive and drive a deburring tool. A pivot bearing is mounted within the housing adjacent the pneumatic motor. A motor support is held within the pivot bearing and extends therefrom where the motor support connects to the pneumatic motor. An air inlet is disposed adjacent the pivot bearing and is communicatively connected thereto. Air for driving the pneumatic motor is directed through the air inlet, and through a hollow portion of the motor support to where air is directed into the pneumatic motor. Because the motor support is supported or contained within the pivot bearing, it follows that the motor support articulates with the pivot bearing and hence the pneumatic motor moves with the articulating motor support.

Abstract: Apparatus and methods are disclosed for controlling the memory controller and, in particular, controlling signaling of the memory controller to a memory via memory interface during a static screen condition. An apparatus includes static image detection logic that is configured to detect when image data being displayed by a display controller is static and to communication detection of static image data to the display controller. The apparatus also includes control logic within the display controller responsive to the static image detection logic, where the control logic is configured to detect a level of a line buffer within the display controller and to send a signal to a memory controller directing the memory controller to issue a signal to a memory to enter a self-refresh mode, thereby turning off at least one memory clocking circuit within the memory controller. A corresponding method is also disclosed.

Abstract: A digital pixel clock generation circuit receives image data and corresponding image presentation time information from at least one external image source. The digital pixel clock generation circuit includes an image presentation timing error determination circuit that produces desired pixel clock frequency control information, such as pixel output clock adjustment control information, based on a difference between an expected presentation time and an actual presentation image time information. A programmable digital waveform generation circuit is programmed based on the produced desired pixel clock frequency and has an input that is responsive to an independent clock source, that is independent from the clock source of the external image source. The programmable digital waveform generation circuit provides a digital representation of an independently generated desired pixel clock which is then output to a digital to analog converter (DAC).

Abstract: Profiling execution of a program. The program is coded in a mode-dependent instruction set. During a profile-quiescent execution interval, the profile circuitry records no profile information. After a triggering event is detected, the profile circuitry commences a profiled execution interval, and records profile information describing every profileable event during that interval. The profiled information includes at least all divergence of execution from sequential execution and processor mode changes not inferable from instruction opcode. The recorded profile information is efficiently tailored to annotate the profiled binary code with sufficient processor mode information to resolve mode-dependency, and indicates contiguous ranges of sequential instructions executed during a profiled interval by low and high boundaries of the contiguous ranges, indicating the high boundary by the address of the last byte.

Abstract: An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

Abstract: Methods and apparatus for matching voltages between two or more circuits within an integrated circuit is disclosed. The apparatus includes a comparator circuit, comparing supply voltages to first and second circuits. The comparator outputs a variable error voltage based on the comparison, the error voltage related to the difference in voltages. The error voltage is supplied to a variable current control circuit that variably sinks one of the supply voltages to a common potential in order to increase the IR drop in the circuit supplying voltage to one of the first and second circuits, thereby affording voltage adjustment in order to match the first and second circuits. A corresponding method is also disclosed.

Abstract: A 6-pin electronic package includes a first side including a pair of first outer pins and a first middle pin, and a second side including a pair of second outer pins and a second middle pin. The first outer pins and the second middle pin are operatively coupled to a first circuit to provide a first function. The second outer pins and the first middle pin are operatively coupled to a second circuit to provide a second function. The 6-pin electronic package can be replaced on a circuit substrate with a first electronic package and a second electronic package that collectively include at least six pins. The 6-pin electronic package and the first and second electronic packages can be interchangeably used on a circuit substrate of an electronic device. The circuit substrate may include any one of the 6-pin electronic package mountable to the circuit substrate, and the first and second electronic packages.

Abstract: A differential serial communication receiver circuit automatically compensates for intrapair skew between received differential signals on a serial differential communication link, with deterministic skew adjustment set during a receiver training period. Intrapair skew refers to the skew within a pair of differential signals, and is hence interchangeable with the term differential skew in the context of this document. During the receiver training period, a training data pattern is received, such as alternating ones and zeros (e.g., a D10.2 pattern as is known in the art), rather than an actual data payload. The differential serial communication receiver circuit includes a differential skew compensation circuit to compensate for intrapair skew.

Abstract: The present disclosure relates to apparatus and methods for measurement of analog voltages in an integrated circuit. In particular, the apparatus includes an on-chip digital-to-analog converter configured to receive a variable digital input code and output a corresponding analog voltage corresponding to the variable digital input code. The apparatus also includes an on-chip comparator circuit configured to receive the analog voltage output by the digital-to-analog converter and a test analog voltage as inputs and to provide an output indicating the test analog voltage. Further, the apparatus includes an on-chip logic operative to determine the test analog voltage based on the output of the comparator circuit. A corresponding method is also disclosed.

Abstract: A copy protection (CP) key used by a sending source, such as a POD, to encrypt content such as audio and/or video information is derived by a first key generator associated with a first processor and is locally encrypted by the first processor using a locally generated bus encryption key to produce a bus encrypted CP key that is sent over a local unsecure bus to a second processor, such as a graphics processor. The second processor decrypts the bus encrypted copy key using a decryption engine to obtain the CP key. The second processor receives the encrypted content and in one embodiment, also uses the same decryption engine to decrypt the encrypted content. The first and second processors locally exchange public keys to each locally derive a bus encryption key used to encrypt the CP key before it is sent over the unsecure bus and decrypt the encrypted CP key after it is sent over the bus.

Abstract: A system and method is provided for synchronizing the presentation of audio data with video data. Audio transport packets are received through a demultiplexer from a multimedia transport stream. A transport stream synchronization manager is used to lock a system time clock, local to the demultiplexer, to a program clock reference provided through the multimedia transport stream. Presentation time stamps are provided with the audio transport packets to indicate when decoded audio data is to be output. A packetized elementary stream synchronization manager maintains synchronization by adding or dropping audio packets from the audio transport packets. If the packetized elementary stream manager is unable to acquire synchronization it must defer synchronization back to the transport stream synchronization manager. Otherwise, processed audio packets are passed to an elementary stream synchronization manager that attempts to synchronize the delivery of audio data through a sample rate conversion of the audio data.