Patents Assigned to Attopsemi Technology Co., Ltd.
  • Patent number: 11615859
    Abstract: An OTP with ultra-low power read can be programmed with a minimum and a maximum program voltage. When programming within the range, the post-program OTP to pre-program resistance ratio can be larger than N, where N>50, so that more sensing techniques, such as single-end sensing, can be used to reduce read current. At least one of the OTP cells can be coupled to a common bitline, which can be further coupled to a first supply voltage lines via a plurality of datalines. The resistance in the at least one OTP cell can be evaluated by strobing at least one comparator output of the discharging bitline/dataline.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: March 28, 2023
    Assignee: Attopsemi Technology Co., LTD
    Inventor: Shine C. Chung
  • Patent number: 11062786
    Abstract: A time-based sensing circuit to convert resistance of a one-time programmable (OTP) element into logic states is disclosed. A one-time programmable (OTP) memory has a plurality of OTP devices. At least one of the OTP devices can have at least one OTP element that is selectively accessible via a wordline and a bitline. The bitline can be coupled a capacitor and the capacitor can be precharged and discharged. By comparing the discharge rate of the capacitor to discharge rate of a reference capacitor in a reference unit (e.g., reference cell, reference resistance, reference selector, etc.), the PRE resistance can be determined larger or smaller than a reference resistance and then converting the OTP element resistance into a logic state.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: July 13, 2021
    Assignee: Attopsemi Technology Co., LTD
    Inventor: Shine C. Chung
  • Patent number: 11011577
    Abstract: An One-Time Programmable (OTP) memory is built in at least one of nano-wire structures. The OTP memory has a plurality of OTP cells. At least one of the OTP cells can have at least one resistive element and at least one nano-wires. The at least one resistive element can be built by an extended source/drain or a MOS gate. The at least one nano-wires can be built on an isolated structure that has at least one MOS gate dividing nano-wires into at least one first active region and a second active region. The first active region can be doped with a first type of dopant and the second active region can be doped with a first or second type of dopant. The OTP element can be coupled to the first active region with the other end coupled to a first supply voltage line. The second active region can be coupled to a second voltage supply line and the MOS gate is coupled to a third voltage supply line.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: May 18, 2021
    Assignee: Attopsemi Technology Co., Ltd
    Inventor: Shine C. Chung
  • Patent number: 10923204
    Abstract: A method of testing an OTP memory is disclosed. An OTP program mechanism that uses heat accelerated electromigration can be fully tested. In one embodiment, an OTP cell's programmability can be tested if an initial OTP element resistance is less than a predetermined resistance, as such insures that sufficient heat can be generated to be programmable. A non-destructive program state, or fake reading 1, can be created by low-voltage programming a cell while reading the same cell at the same time. Accordingly, alternative 0s and 1s patterns can be generated to fully test every functional block of an OTP memory.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: February 16, 2021
    Assignee: Attopsemi Technology Co., LTD
    Inventor: Shine C. Chung
  • Patent number: 10916317
    Abstract: Programmable resistive memory can be fabricated with a non-single-crystalline silicon formed on a flexible substrate. The non-single-crystalline silicon can be amorphous silicon, low-temperature polysilicon (LTPS), organic semiconductor, or metal oxide semiconductor. The flexible substrate can be glass, plastics, paper, metal, paper, or any kinds of flexible film. The programmable resistive memory can be PCRAM, RRAM, MRAM, or OTP. The OTP element can be a silicon, polysilicon, organic or metal oxide electrode. The selector in a programmable resistive memory can be a MOS or diode with top gate, bottom gate, inverted, staggered, or coplanar structures.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: February 9, 2021
    Assignee: Attopsemi Technology Co., LTD
    Inventor: Shine C. Chung
  • Patent number: 10770160
    Abstract: Architecture, design, structure, layout, and method of forming a Programmable Resistive Device (PRD) memory in standard cell library are disclosed. The PRD memory has a plurality of PRD cells. At least one of the PRD cells can have a PRD element coupled to a first supply voltage line and coupled to a second supply voltage line through a program selector. The PRD cells reside in a standard cell library and following most of the standard cell design and layout guidelines.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: September 8, 2020
    Assignees: Attopsemi Technology Co., LTD, Renesas Electronics Corporation
    Inventors: Shine C. Chung, Koji Nii
  • Patent number: 10726914
    Abstract: A time-based sensing circuit to convert resistance of a programmable resistive element into logic states is disclosed. A programmable resistive memory has a plurality of programmable resistive devices. At least one of the programmable resistive devices can have at least one programmable resistive element (PRE) that is selectively accessible via a wordline and a bitline. The bitline can be coupled a capacitor and the capacitor can be precharged and discharged. By comparing the discharge rate of the capacitor to discharge rate of a reference capacitor in a reference unit (e.g., reference cell, reference resistance, reference selector, etc.), the PRE resistance can be determined larger or smaller than a reference resistance and then converting the PRE resistance into a logic state.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: July 28, 2020
    Assignee: ATTOPSEMI TECHNOLOGY CO. LTD
    Inventor: Shine C. Chung
  • Patent number: 10586593
    Abstract: Building programmable resistive devices in contact holes at the crossover of a plurality of conductor lines in more than two vertical layers is disclosed. There are plurality of first conductor lines and another plurality of second conductor lines that can be substantially perpendicular to each other, though in two different vertical layers. A diode and/or a programmable resistive element can be fabricated in the contact hole between the first and second conductor lines. The programmable resistive element can be coupled to another programmable resistive device or shared between two programmable devices whose diodes conducting currents in opposite directions and/or coupled to a common conductor line. The programmable resistive memory can be configured to be programmable by applying voltages to conduct current flowing through the programmable resistive element to change its resistance for a different logic state.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: March 10, 2020
    Assignee: Attopsemi Technology Co., LTD
    Inventor: Shine C. Chung
  • Patent number: 10586832
    Abstract: An One-Time Programmable (OTP) memory is built in at least one of nano-wire structures. The OTP memory has a plurality of OTP cells. At least one of the OTP cells can have at least one resistive element and at least one nano-wires. The at least one resistive element can be built by an extended source/drain or a MOS gate. The at least one nano-wires can be built on a common well or on an isolated structure that has at least one MOS gate dividing nano-wires into at least one first active region and a second active region.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: March 10, 2020
    Assignee: Attopsemi Technology Co., LTD
    Inventor: Shine C. Chung
  • Patent number: 10535413
    Abstract: A programmable resistive memory has a plurality of programmable resistive devices (PRD) and at least one sensing circuit. The at least one of the programmable resistive device can include at least one programmable resistive element (PRE). The sensing circuit can include one PRD unit and a reference unit. Each unit has at least one capacitor to charge to a second supply voltage line and to discharge to the first supply voltage line through the PRE and the reference element, respectively. The capacitors are also coupled to comparators to monitor discharging voltages with respect to a reference voltage. By comparing the time difference when the comparators change their outputs, the magnitude of the PRE resistance with respect to the reference element resistance can be determined and converted into logic states.
    Type: Grant
    Filed: April 14, 2018
    Date of Patent: January 14, 2020
    Assignee: Attopsemi Technology Co., LTD
    Inventor: Shine C. Chung
  • Patent number: 10249379
    Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuses. At least one portion of the electrical fuse can have at least one extended area to accelerate programming. An extended area is an extension of the fuse element beyond contact or via longer than required by design rules. The extended area also has reduced or substantially no current flowing through. The program selector can be at least one MOS. The OTP device can have the at least one OTP element coupled to at least one diode in a memory cell.
    Type: Grant
    Filed: September 13, 2014
    Date of Patent: April 2, 2019
    Assignee: Attopsemi Technology Co., LTD
    Inventor: Shine C. Chung
  • Patent number: 10229746
    Abstract: A method of programming electrical fuses reliably is disclosed. If a programming current exceeds a critical current, disruptive mechanisms such as rupture, thermal runaway, decomposition, or melt, can be a dominant programming mechanism such that programming is not be very reliable. Advantageously, by controlled programming where programming current is maintained below the critical current, electromigration can be the sole programming mechanism and, as a result, programming can be deterministic and very reliable. In this method, fuses can be programmed in multiple shots with progressive resistance changes to determine a lower bound that all fuses can be programmed satisfactorily and an upper bound that at least one fuse can be determined failed. If programming within the lower and upper bounds, defects due to programming can be almost zero and, therefore, defects are essentially determined by pre-program defects.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: March 12, 2019
    Assignee: Attopsemi Technology Co., LTD
    Inventor: Shine C. Chung
  • Patent number: 10192615
    Abstract: An One-Time Programmable (OTP) memory is built in at least one of semiconductor fin structures. The OTP memory has a plurality of OTP cells. At least one of the OTP cells can have at least one resistive element and at least one fin. The at least one resistive element can be built by an extended source/drain or a MOS gate. The at least one fin can be built on a common well or on an isolated structure that has at least one MOS gate dividing fins into at least one first active region and a second active region.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: January 29, 2019
    Assignee: Attopsemi Technology Co., LTD
    Inventor: Shine C. Chung
  • Patent number: 10127992
    Abstract: A method of programming electrical fuses reliably is disclosed. If a programming current exceeds a critical current, disruptive mechanisms such as rupture, thermal runaway, decomposition, or melt, can be a dominant programming mechanism such that programming is not be very reliable. Advantageously, by controlled programming where programming current is maintained below the critical current, electromigration can be the sole programming mechanism and, as a result, programming can be deterministic and very reliable. In this method, fuses can be programmed in multiple shots with progressive resistance changes to determine a lower bound that all fuses can be programmed satisfactorily and an upper bound that at least one fuse can be determined failed. If programming within the lower and upper bounds, defects due to programming can be almost zero and, therefore, defects are essentially determined by pre-program defects.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: November 13, 2018
    Assignee: Attopsemi Technology Co., Ltd.
    Inventor: Shine C. Chung
  • Patent number: 9881970
    Abstract: A programmable resistive memory having a plurality of programmable resistive cells. At least one of the programmable resistive cell includes a programmable resistive element and at least one selector. The selector can be built in at least one fin structure and at least one active region divided by at least one MOS gate into a first active region and a second active region. The first active region can have a first type of dopant to provide a first terminal of the selector. The second active region can have a first or a second type of dopant to provide a second terminal of the selector. The MOS gate can provide a third terminal of the selector. The first terminal of the selector can be coupled to the first terminal of the programmable resistive element. The programmable resistive element can be programmed by conducting current flowing through the selector to thereby change the resistance state.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: January 30, 2018
    Assignee: Attopsemi Technology Co. LTD.
    Inventor: Shine C. Chung
  • Patent number: 9824768
    Abstract: An integrated One-Time Programmable (OTP) memory to emulate an Multiple-Time Programmable (MTP) memory with a built-in program count tracking and block address mapping is disclosed. The integrated OTP memory has at least one non-volatile block register and count register to respectively store block sizes and program counts for different block/count configurations. The count register can be programmed before each round of programming occurs to indicate a new block for access. The integrated OTP memory also can generate a block address based on values from the count and block registers. By combining the block address with the lower bits of an input address, a final address can be generated and used to access different blocks (associated with different program counts) in the OTP memory to mimic an MTP memory.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: November 21, 2017
    Assignee: ATTOPSEMI TECHNOLOGY CO., LTD
    Inventor: Shine C. Chung
  • Patent number: 9818478
    Abstract: Building programmable resistive devices in contact holes at the crossover of a plurality of conductor lines in more than two vertical layers is disclosed. There are plurality of first conductor lines and another plurality of second conductor lines that can be substantially perpendicular to each other, though in two different vertical layers. A diode and/or a programmable resistive element can be fabricated in the contact hole between the first and second conductor lines. The programmable resistive element can be coupled to another programmable resistive device or shared between two programmable devices whose diodes conducting currents in opposite directions and/or coupled to a common conductor line. The programmable resistive memory can be configured to be programmable by applying voltages to conduct current flowing through the programmable resistive element to change its resistance for a different logic state.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: November 14, 2017
    Assignee: Attopsemi Technology Co., LTD
    Inventor: Shine C. Chung
  • Patent number: 9767915
    Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors with at least one heat sink or heater to assist programming for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The heat sink can be at least one thin oxide area, extended OTP element area, or other conductors coupled to the OTP element to assist programming. A heater can be at least one high resistance area such as an unsilicided polysilicon, unsilicided active region, contact, via, or combined in serial, or interconnect to generate heat to assist programming. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: September 19, 2017
    Assignee: Attopsemi Technology Co., LTD
    Inventor: Shine C. Chung
  • Patent number: 9754679
    Abstract: An OTP (One-Time Programmable) memory including OTP memory cells that utilize OTP elements fabricated in CMOS FinFET processes. The OTP memory cell can also include at least one selector built upon at least one fin structure that has at least one CMOS gate to divide the fin structure into at least a first and a second active region. The selector can be implemented as a MOS device, dummy-gate diode, or Schottky diode as selector such as by using different types of source/drain implants. The OTP element that can be implemented as polysilicon, silicided polysilicon, CMOS metal gate, any layers of metal as interconnect, or active region. In one embodiment, the OTP element can be a fin structure and can be built upon the same fin structure as the at least one of the selector. By using different source/drain implant schemes on the two active regions, the selector can be turned on as MOS device, MOS device and/or diode, dummy-gate diode, or Schottky diode.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: September 5, 2017
    Assignee: Attopsemi Technology Co., Ltd
    Inventor: Shine C. Chung
  • Patent number: 9711237
    Abstract: A method of programming electrical fuses reliably is disclosed. If a programming current exceeds a critical current, disruptive mechanisms such as rupture, thermal runaway, decomposition, or melt, can be a dominant programming mechanism such that programming is not be very reliable. Advantageously, by controlled programming where programming current is maintained below the critical current, electromigration can be the sole programming mechanism and, as a result, programming can be deterministic and very reliable. In this method, fuses can be programmed in multiple shots with progressive resistance changes to determine a lower bound that all fuses can be programmed satisfactorily and an upper bound that at least one fuse can be determined failed. If programming within the lower and upper bounds, defects due to programming can be almost zero and, therefore, defects are essentially determined by pre-program defects.
    Type: Grant
    Filed: September 13, 2014
    Date of Patent: July 18, 2017
    Assignee: Attopsemi Technology Co., Ltd.
    Inventor: Shine C. Chung