Abstract: A plasma processing apparatus includes a chamber (20) and a target (25) above the chamber (20). The surface of the target (25) contacts the processing area of the chamber (20). The chamber (20) includes an insulating sub-chamber (21) and a first conductive sub-chamber (22), which are superposed. The first conductive sub-chamber (22) is provided under the insulating sub-chamber (21). The insulating sub-chamber (21) is made of insulating material, and the first conductive sub-chamber (22) is made of metal material. A Faraday shield component (10) which is made of metal material or insulating material electroplated with conductive coatings and includes at least one slit is provided in the insulating sub-chamber (21). An inductance coil (13) surrounds the exterior of the insulating sub-chamber (21). The problem about the wafer contamination due to particles formed on the surface of the coil during the sputtering process can be solved by using the plasma processing apparatus.

Abstract: A method for applying power to target material in a magnetron sputtering process is provided. The method includes: 10) connecting a main power supply and a maintaining power supply to the target material (2) respectively; 20) applying a particular main power in the form of pulses to the target material (2) by the main power supply; applying a particular maintaining power which is smaller than the main power to the target material (2) by the maintaining power supply at least during the pulse interval time (t2) of the main power supply, so as to maintain a glow discharge procedure of the sputtering process during the purse interval time (t2) of the main power supply. The method for applying power to target material can obviously enhance the metal ionization rate while the process stability and controllability are guaranteed.

Abstract: The present invention provides a semiconductor structure, which comprises a substrate, a semiconductor base, a cavity, a gate stack, sidewall spacers, source/drain regions and a contact layer; wherein, the gate stack is located on the semiconductor base, the sidewall spacers are located on sidewalls of the gate stack, the source/drain regions are embedded within the semiconductor base and located on both sides of the gate stack, the cavity is embedded within the substrate, and the semiconductor base is suspended over the cavity, the thickness in the middle portion of the semiconductor base is greater than the thicknesses at both ends of the semiconductor base in a direction along the gate length, and both ends of the semiconductor base are connected with the substrate in a direction along the gate width; the contact layer covers exposed surfaces of the source/drain regions.

Abstract: A plasma processing device includes a first electrode plate (3), a second electrode plate (4), a matching device (8), a power distribution device (9) and a power supply device (1). The first electrode plate (3) includes at least two sub-electrode plates (31, 32) insulated from each other; the power supply device (1) is connected to the power distribution device (9) via the matching device (8); the power distribution device (9) is connected to the first electrode plate (3) for inputting and distributing the power of the power supply device (1) to each of the sub-electrode plates (31, 32); the power distribution device (9) at least includes capacitors (C1, C2) and/or inductances (L1, L2).

Abstract: The present invention provides a semiconductor structure, which comprises a substrate, a semiconductor base, a cavity, a gate stack, sidewall spacers, source/drain regions and a contact layer; wherein, the gate stack is located on the semiconductor base, the sidewall spacers are located on sidewalls of the gate stack, the source/drain regions are embedded within the semiconductor base and located on both sides of the gate stack, the cavity is embedded within the substrate, and the semiconductor base is suspended over the cavity, the thickness in the middle portion of the semiconductor base is greater than the thicknesses at both ends of the semiconductor base in a direction along the gate length, and both ends of the semiconductor base are connected with the substrate in a direction along the gate width; the contact layer covers exposed surfaces of the source/drain regions.

Abstract: The present invention provides a semiconductor structure and a method for manufacturing the same. The method comprises: providing a substrate, forming sequentially a first high-k dielectric layer, an adjusting layer, a second high-k dielectric layer and a metal gate on the substrate, etching the first high-k dielectric layer, the adjusting layer, the second high-k dielectric layer and the metal gate to form a gate stack. Accordingly, the present invention further provides a semiconductor structure. The present invention proposes to arrange an adjusting layer between two layers of high-k dielectric layer, which effectively avoids reaction of the adjusting layer with the metal gate because of their direct contact, so as to maintain the performance of semiconductor devices.

Abstract: The present invention provides a semiconductor structure and a method for manufacturing the same. The method comprises the following steps: providing a semiconductor substrate, forming sequentially a gate dielectric layer, a metal gate, a CMP stop layer, and a poly silicon layer on the semiconductor substrate; etching the gate dielectric layer, the metal gate, the CMP stop layer and the poly silicon layer to form a gate stack; forming a first interlayer dielectric layer on the semiconductor substrate to cover the gate stack on the semiconductor substrate and the portions on both sides of the gate stack; performing a planarization process, such that the CMP stop layer is exposed and flushed with the upper surface of the first interlayer dielectric layer. Accordingly, the present invention further provides a semiconductor structure.

Abstract: The present invention provides an electrostatic chuck, which includes a base (102) and an electrode (401, 402) arranged inside the base, the electrostatic chuck further includes a charge releasing unit, the electrode can be selectively connected to a power supply arranged outside the electrostatic chuck or connected to the charge releasing unit in order to connect to the power supply to obtain electric energy during the process and connect to the charge releasing unit to release remaining charges on the electrode and then to remove remaining charges on the work piece held on the electrostatic chuck during the charge releasing process. A method for removing remaining charges on the electrostatic chuck is also provided, and the method can release the remaining charges on the electrode and the wafer more thoroughly and rapidly to eliminate the appearance of wafer adherence and wafer crack, so as to reduce possibility of the interruption of the process and improve the production efficiency and yield.

Abstract: The present invention provides a device and a method for controlling a DC bias of a RF discharge system. Said device comprises a DC bias detection module (302), a mode selection module (301), a DC bias controlling module (303) and a RF power providing module (304). The mode selection module (301) receives a parameter and a type of the parameter. If the type of the parameter is representative of voltage, the DC bias controlling module (303) calculates a power value according to the voltage-related representative parameter and the detected DC bias value, and the RF power providing module (304) provides power according to the calculated power value. If the type of the parameter is representative of power, the RF power providing module (304) provides power according to the power-related representative parameter.

Abstract: A deep-trench silicon etching apparatus, including a reaction chamber and a gas source cabinet, the gas source cabinet is connected to the reaction chamber via two independently controlled gas paths; wherein, a first gas path is used to introduce process gas for etch step from the gas source cabinet into the reaction chamber; a second gas path is used to introduce process gas for deposition step from the gas source cabinet into the reaction chamber. The present invention is used to solve the problems of gas mixture and gas delay occurring when process steps are switched.

Abstract: A method of online predicting maintenance of an apparatus is disclosed. Using an optical emission spectroscopy (OES) positioned on the apparatus and the change of emission spectrum intensity detected by the OES in the process, according to the detected results, measuring the parameter in the process, the function relation between the process parameter and spectrum intensity is acquired. A control threshold is decided by the processing requirement to the apparatus. When the parameter exceeds the control threshold, maintenance to the etching apparatus is engaged in order to avoid processing error caused by frequent shutdown or deficient maintenance which is estimated by experience, and hence decreasing the cost and increasing processing efficiency of substrates (such as silicon wafers) without changing apparatus and adding other online sensor, and improving production rate by avoiding waste substrates caused by error processing results.

Abstract: A plasma processing apparatus (5) comprises an outer shell (51) which is provided with a reaction chamber (52) in the interior, a bottom electrode which is arranged in the reaction chamber (52) and a cantilever support device (53) which goes through the outer shell (51) and supports the bottom electrode. The cantilever support device (53) is pivotally mounted on the side wall of the outer shell (51) and can rotate in the outer shell (51). The plasma processing apparatus (5) further comprises a locating device so as to selectively fix the relative position of the cantilever support device (53) and the outer shell (51).