Abstract: A multistandard RF transceiver is disclosed that may optionally include selectable mixers; selectable amplifiers; a configurable analog filter; and a configurable analog to digital converter. The multistandard RF transceiver may also include a data interface for sending data to a host controller and a control interface for receiving configuration commands from the host controller. The configuration commands identify a wireless standard that is to be implemented by the RF receiver. An RF processor processes an RF signal wherein the processed RF signal is output to the host controller on the data interface.

Abstract: A phase synchronous multiple LC tank oscillator includes a plurality of oscillator stages that are configured to oscillate synchronously. The phase of each of the plurality of oscillator stages is substantially the same and the plurality of oscillators are inductively coupled. The synchronous oscillation is substantially caused by magnetic coupling. The oscillator stages may be electrically coupled during a first time period and the electrical coupling and disconnected or reduced during a second time period.

Abstract: A complex filter includes an I channel having a first I channel output and a second I channel output and a Q channel having a first Q channel output and a second Q channel output. The second I channel output is input to the Q channel through a first passive network and wherein the second Q channel output is input to the I channel through a second passive network.

Abstract: A cascaded voltage controlled oscillator is described that includes a first oscillator stage having a first oscillator stage first input, a first oscillator stage second input and a first oscillator stage output. A second oscillator stage includes a second oscillator stage input and a second oscillator stage output wherein the first oscillator stage output is input to the second oscillator stage input and wherein the second oscillator stage output is fed back to the first oscillator stage second input. A third oscillator stage includes a third oscillator stage input and a third oscillator stage output wherein the second oscillator stage output is fed to the third oscillator stage input.

Abstract: A technique is disclosed for providing a charge pump circuit for phase locked loop (PLL) to reduce mismatch of up/down currents and feed-through of up/down currents to voltage output. Elimination of feed-through of the input signal may be achieved by using differential switches (M1 and M2, and M3 and M4) based on DC reference voltage in the charge pump and also eliminate the mismatch of up/down currents in a wide voltage output range by applying a new replica biasing using feedback.

Abstract: A phase synchronous multiple LC tank oscillator includes a plurality of oscillator stages configured to oscillate synchronously. The phase of each of the plurality of oscillator stages is substantially the same.

Abstract: A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.

Abstract: A cascaded voltage controlled oscillator is described that includes a first oscillator stage having a first oscillator stage first input, a first oscillator stage second input and a first oscillator stage output. A second oscillator stage includes a second oscillator stage input and a second oscillator stage output wherein the first oscillator stage output is input to the second oscillator stage input and wherein the second oscillator stage output is fed back to the first oscillator stage second input. A third oscillator stage includes a third oscillator stage input and a third oscillator stage output wherein the second oscillator stage output is fed to the third oscillator stage input.

Abstract: A system and method are disclosed for generating a variable frequency output. A voltage controlled oscillator (VCO) is used. The VCO comprises a plurality of aggregate capacitor circuits, wherein each of the aggregate capacitor circuits has a collective capacitance, at least two of the collective capacitances have different values, and each of the aggregate capacitor circuits includes one or more individual capacitors wherein each of the individual capacitors are substantially the same size. The VCO further comprises a plurality of switches configured to select one or more aggregate capacitor circuits from among the plurality of aggregate capacitor circuits to form a discretely variable capacitor network having a discretely variable capacitance, wherein the discretely variable capacitor network is configured to cause an oscillator to generate a variable frequency as a result of the discretely variable capacitance.

Abstract: A system and method are disclosed for generating a synthesized signal. A frequency synthesizer is used. The frequency synthesizer includes an input interface configured to receive an input signal having a reference frequency; a phase locked loop (PLL) coupled to the input interface, having a fractional N configuration and comprises a voltage controlled oscillator; wherein the voltage controlled oscillator is configured to generate the synthesized signal; and the voltage controlled oscillator includes an on-chip inductor.

Abstract: A sigma delta modulator system and a method for modulating a signal are described. The sigma delta modulator includes a plurality of cascading stages, an output coupled to the plurality of the cascading stages via a plurality of feedback connections, and a feedforward connection coupled between a selected one of the plurality of cascading stages and a point closer to the output interface of the sigma delta modulator.

Abstract: A quadrature signal generator includes a polyphase filter where four resistive elements and four variable capacitive elements are connected alternately in series to form a loop; and a phase corrector that variably controls the capacitance of the variable capacitive elements.

Abstract: A cascaded voltage controlled oscillator is described that includes a first oscillator stage having a first oscillator stage first input, a first oscillator stage second input and a first oscillator stage output. A second oscillator stage includes a second oscillator stage input and a second oscillator stage output wherein the first oscillator stage output is input to the second oscillator stage input and wherein the second oscillator stage output is fed back to the first oscillator stage second input. A third oscillator stage includes a third oscillator stage input and a third oscillator stage output wherein the second oscillator stage output is fed to the third oscillator stage input.

Abstract: A power amplifier includes drains and sources of a plurality of transistors connected to each other to produce a plurality of common drains and a plurality of common sources, wherein the common drains are connected at a common drain point and wherein the common drain point is connected via an RF choke to a power supply voltage terminal and wherein the common sources are grounded; an output terminal connected to the RF choke; a plurality of bias terminals each coupled via a resistor to the gate of one of the plurality of transistors wherein each of the gates of the plurality of transistors is also capacitively coupled to a radio frequency input.

Abstract: A system and method are disclosed for providing a FSK demodulator using DLL and a demodulating method which detects a time order of the rising edges of square waves that correspond to two modulation frequencies and an in-between frequency and demodulates the relevant frequencies into data. The FSK demodulator includes a band-pass filter, an amplitude limiter for converting a waveform of the frequency filtered into a square wave, a delay line for receiving the square wave from the amplitude limiter and delaying the square wave for a delay time, a delayed flip-flop (DFF) for receiving an output signal from the amplitude limiter and an output signal from the delay line, determining which rising edge of the two input signals is earlier at a given time, and outputting the result of the determination as data, and a DLL circuit that locks the delay time of the delay line.

Abstract: A technique is disclosed for providing a charge pump circuit for phase locked loop (PLL) to reduce mismatch of up/down currents and feed-through of up/down currents to voltage output. Elimination of feed-through of the input signal may be achieved by using differential switches (M1 and M2, and M3 and M4) based on DC reference voltage in the charge pump and also eliminate the mismatch of up/down currents in a wide voltage output range by applying a new replica biasing using feedback.

Abstract: A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.

Abstract: DC offset canceling is disclosed. A DC level fixing signal generator receives feedback input of two output signals from a mixer and generates a level fixing control signal to fix the DC level of the two output signals according to the input values. A DC offset canceling signal generator receives feedback input of two output signals from the mixer and generates offset canceling control signals to cancel the relative difference between the DC levels of the two output signals according to the input values. A DC level fixing and offset canceling circuit fixes the DC level of each of the two output signals from the mixer and cancels the relative difference between the DC levels of the two output signals according to the level fixing control signal and the offset canceling control signals.

Abstract: A quadrature signal generator includes a polyphase filter where four resistive elements and four variable capacitive elements are connected alternately in series to form a loop; and a phase corrector that variably controls the capacitance of the variable capacitive elements.

Abstract: A power amplifier includes drains and sources of a plurality of transistors connected to each other to produce a plurality of common drains and a plurality of common sources, wherein the common drains are connected at a common drain point and wherein the common drain point is connected via an RF choke to a power supply voltage terminal and wherein the common sources are grounded; an output terminal connected to the RF choke; a plurality of bias terminals each coupled via a resistor to the gate of one of the plurality of transistors wherein each of the gates of the plurality of transistors is also capacitively coupled to a radio frequency input.