Abstract: Output members in a matrix relationship having x and y inputs respectively receive signals in first and second pluralities cumulatively representing a digital value. These signals are decoded and are respectively introduced to the x and y inputs to activate a particular output member common to a selected x row and a selected y column. The output members in the preceding rows and preceding the activated output member in the selected row are also activated. Three-transistor (all of the same type) current sources provide constant currents to the activated output members. In each current source, a first transistor provides the constant current, a second transistor in each current source constitutes a switch operative in response to binary input signals, and a third transistor receives the constant current dependent upon the binary input to the second transistor.
Abstract: First binary bits are read synchronously relative to clock signals (e.g. 125 MH.sub.z) from first memory positions and second binary bits are read from, or written in, second memory positions asynchronously relative to the clock signals without affecting the reading of the first memory bits. For synchronously reading the first bits, a plurality of channels are sequentially activated at a suitable frequency (e.g. 25 megahertz). Information from pairs of data lines are introduced into a pair of buses at the clock frequency. The information in the buses is sampled upon the occurrence of the first polarity in synchronizing signals having frequency (e.g. 62.5 MH.sub.3) derived from the clock signals and is prolonged and evaluated in a first pair of output lines upon the occurrence of the second polarity in the synchronizing signals. The information being evaluated is introduced to such output lines during the occurrence of the first polarity in the synchronizing signals.
Abstract: Input and reference voltages are respectively applied to the control elements of first and second transistors. This causes a substantially constant current to be divided between the first and second transistors in first time periods. In second time periods alternating with the first periods, the reference voltage is also applied to the control element of the first transistor to produce a current representation of the reference voltage. This causes the first and second transistors respectively to produce in the second periods voltages dependent only upon their relative characteristics. These voltages are introduced in the second periods to first and second capacitances to charge the capacitances when first switches such as transistors are closed. Subsequently in the second periods, the charges in the first and second capacitances are respectively transferred to third and fourth capacitances to charge the third and fourth capacitances.
Abstract: A plurality of members, each constructed to produce a substantially constant current when energized, are disposed electrically in a matrix defined by a plurality of rows and a plurality of columns. A plurality of signals cumulatively represent a digital value. Each of the signals has logic levels respectively coding for binary "1" and binary "0" and each has an individual binary significance. The binary signals of intermediate binary significance are decoded to activate an individual rows. The binary signals of high binary significance are decoded to activate an individual column. The member common to the activated row and the activated column then receives a substantially constant current, as do all of the members of lower binary signficance than such common member. The signals of lowest binary significance are also decoded to produce a current having a magnitude indicative of the binary value coded by such signals.
Abstract: An unknown analog signal is compared in amplitude with the signal from a digital-to-analog (D-A) converter. The converter, preferably monotonic, may be at least partially formed from a plurality of switches connected in a recursive array to define sub-sets having a recurrent relationship. An adjustable-gain amplifier produces a difference signal having an amplitude indicating the amplitude comparison. A flash converter converts the difference signal to binary signals. These binary signals are modified and fed back to the D-A converter to obtain from this converter an output signal having an amplitude approximating the amplitude of the unknown analog signal. A plurality of successive approximations of the analog signal may be provided in this manner. In at least one (1) of these approximations, the gain of the amplifier may be increased to increase the sensitivity of the approximation by increasing the gain of the difference signal.
Abstract: A variable electrical current in a first winding on a magnetizable core produces a magnetomotive force in the core. A second core winding produces an opposing magnetomotive force digitally adjustable periodically by a third core winding, a pair of switches and a flip-flop coupled to a center tap for alternately closing such switches when triggered to opposite states. The flip-flop is triggered between opposite states when the third winding current reaches a particular magnitude. In each cycle, the time differences for producing the particular magnitudes and the opposite polarities are dependent upon the remanent core flux. Such time differences are counted digitally upwardly and downwardly for opposite polarities. The second winding current is adjusted digitally in each cycle in a direction to minimize such count. The magnitudes of successive adjustments may be compared periodically by adaptive tracking techniques to control the magnitudes of subsequent adjustments.
Abstract: A digital-to-analog converter includes a decoding network and a plurality of output members such as capacitors. The decoding network receives a plurality of binary signals individually having logic levels respectively coding for binary "1" and binary "0" and individually coding for a binary value of an individually weighted significance and cumulatively coding for an analog value. The network decodes the logic levels of the binary signals and activates output members in accordance with such decoding. As the analog value coded by the logic levels of the binary signals increases, the output members previously activated in the plurality remain activated and other output members in the plurality become activated. The decoding network and the output members are disposed on an integrated circuit chip. Dependent upon their positioning on the chip, the output members have different characteristics which cause errors to be produced in the analog signal, particularly at low analog values.
Abstract: An apparatus and method of synchronizing data systems having different clock frequencies at a particular address. A first device receives first and second parallel data and outputs first serial data at a first particular clock frequency. A second device outputs second parallel data at a second particular clock frequency that is a submultiple at an integer "n" of the first particular clock frequency. The second parallel data is outputted in groups of "n" pieces of data. The address is combined with the integer "n" until the combination passes through a particular numerical value. This produces a first signal representative of the combination passing through the particular numerical value and a second signal representing an offset position less than "n" relative to the first serial data.
Abstract: First and second reference voltages of different value are introduced to opposite ends of a first line disposed on an IC chip and made from a suitable material (e.g. ion-implanted polysilicon). An input voltage having a value between such reference voltages is provided on a second line on the chip. The second line may be substantially parallel to the first line and made from a suitable material (e.g. polysilicon heavily implanted with ions) to provide an identical voltage at every line position. Bridging layers substantially perpendicularly disposed between the lines at progressive positions on the lines may be made from polysilicon heavily implanted with ions. The magnitudes of the line and reference voltages at each bridging layer are compared in a differential amplifier to produce a signal with a polarity dependent upon such relative magnitudes. The signals from the differential amplifiers are combined in pluralities of logical networks.
Abstract: Sub-sets of switches are provided each having a number of switches directly related to an individual bit in a binary coded input word. Signals representing the individual bits are introduced to the switches in the different sub-sets to obtain switch conductivities in accordance with such binary bits. The switches are connected in a repetitive array to provide paths through the conductive ones of the switches. The switches are connected to output members and a line to introduce the current through the output members to the line in accordance with the pattern of switch conductivities. This provides for progressive increases in the number of the output members connected to the line, ad for a continued connection to the line of output members previously connected to the line, with progressive increases in the binary value. The cumulative current through the line is indicative of the analog value.
Abstract: A converter converts to an analog value a plurality of digital signals each having characteristics representing an individual digital value. A plurality of switches are disposed in sets with the switches in each set being responsive to an individual one of the digital signals. The number of switches in each set is related to the digital significance of the set, preferably on an inverse basis. The switches are connected in a repetitive array to output members and a line to provide for the connection for progressive ones of the members to the output line in accordance with the pattern of the switches in the conductive and non-conductive states in representation of progressive increases in the digital value. The repetitive also provides, with such progressive increases in the digital values, output members previously connected to the line. The repetitive array may be responsive to the digital signals in a single delay time.
Abstract: A variable input voltage is periodically introduced in first time periods to an amplifier such as a differential amplifier to obtain an output from the amplifier. The amplifier may receive a reference voltage at one input terminal and the input voltage at a second input terminal in the first time periods. The input to the amplifier is periodically shorted in second time periods alternating with the first time periods so that the reference voltage is applied to both input terminals. Any offset voltage from the amplifier in the second time period may be converted to a binary signal to indicate the polarity of the offset voltage. The binary signal may be introduced to a storage member such as a capacitance. The capacitance accumulates energy in accordance with the characteristics of the binary signal in successive ones of the second time periods. The energy in the capacitance is introduced to the output terminals of the amplifier in a direction to compensate for the offset voltage in the amplifier.
Abstract: A digital value represented by first and second pluralities of signals is converted into an analog value represented by an analog signal. The converter and the associated circuitry described above are preferably disposed on an integrated circuit chip formed from MOS transistors. Circuitry provides output currents of optimal waveforms from the digital-to-analog converters for driving stages subsequent to such converters. The circuits of this invention are advantageous because they operate satisfactorily at frequencies in excess of eighty-five megahertz (85 mhz). The circuits facilitate the production of the signals at such high frequencies by employing the distributed capacitances in a first transistor to expedite the response of a second transistor to binary input signals introduced to the first transistor.
Abstract: A reference generator is used in a digital-to-analog converter to provide for a replication of colors in accordance with binary information introduced to the converter. The generator is responsive to binary signals each having first and second logic levels respectively representing binary "1" and binary "0" and each representing a different one of the binary colors red, green and blue. Each of the binary signals is introduced to an individual one of transistors in a first plurality. An energizing voltage is also introduced to the transistors to obtain a flow of current through such transistors in accordance with the logic levels of such input signals and the magnitude of the energizing voltage. A substantially constant current is provided at first particular times and a reference voltage is provided at other times. An impedance may be common to the circuit for the substantially constant current and the reference voltage.
Abstract: First and second lines respectively receive first and second complementary input signals representing a binary bit. Each of the input signals has first and second logic levels respectively corresponding to a binary "1" and a binary "0". The input signals produce a current through a load in accordance with the relative logic levels of the first and second input signals. The difference between the logic levels of the input signals is amplified and introduced as a negative feedback to a particular one of the first and second lines in accordance with the relative logic levels of the signals on the lines. The feedback causes a current to be produced in the load with a polarity opposite to the polarity of the current produced in the load by the input signals and with a magnitude less than the magnitude of the current produced in the load by the input signals.
Abstract: An integrated circuit chip has circuitry for converting a binary coded value to an analog value. The chip includes first and second matrices each defined by rows and columns. The rows and columns have sources at different positions for producing currents in response to binary signals coding for the binary value. Each row in the first matrix is connected to a row in the second matrix on a reverse-image basis. For example, if each matrix has thirty two (32) rows, rows 1 and 32 in the first matrix are respectively connected to rows 32 and 1 in the second matrix. The rows in the matrices are sequentially selected in a pattern providing particular convergences and divergences of successive paris of such rows in each matrix. Such sequential selection provides progressive convergences and then progressive divergences of the rows in each of the successive pairs in each matrix about the center line as a reference. Such progressive convergences and divergences may occur in at least a pair of successive cycles.
Abstract: A digital value represented by first and second pluralities of signals is converted into an analog value represented by an analog signal. The converter and the associated circuitry described above are preferably disposed on an integrated circuit chip formed from C-MOS transistors. Circuitry is also provided for converting signal levels from TTL logic devices external to the chip into signals for operating the C-MOS transistors on the chip by adjusting the voltages from the TTL logic devices into voltages optimal for operating the C-MOS transistors. The circuits of this invention are advantageous because they operate satisfactorily at frequencies in excess of eighty-five megahertz (85 mhz).
Abstract: First and second switches such as transistors are connected to a charge storage member such as a capacitance. The capacitance is charged through the first transistor from a positive supply when the transistor becomes conductive. The capacitances is discharged through the second transistor to a reference potential such as ground when the second transistor becomes conductive. The conductivities of the first and second transistors are controlled by pulses from a pulse source such as a transformer. The transformer primary produces a pulse of one polarity upon the occurrence of the leading edge of an input signal and a pulse of an opposite polarity upon the occurrence of the trailing edge of the input signal. Two secondary windings are respectively connected in opposite polarities to the bases of the first and second transistors to provide for the conductivity of only one of the transistors at any one time.
Abstract: A first matrix relationship is defined by a plurality of switches operative in first and second states in accordance with the logic levels of binary signals introduced to the switches. The switches in the matrix relationship receive binary signals of relatively high binary significance. An activating line is connected to the matrix relationship to activate storage members, such as capacitors, connected to the matrix relationship. The number of storage members energized by the activating line at each instant is related to the value coded by the logic levels of the binary signals introduced to the matrix relationship. For increasing binary values, the storage members previously energized in the plurality by the activating line continue to be energized and additional storage members in the plurality are energized. An interpolating line is also provided in the first matrix relationship.
Abstract: Signals representing individual digital values are introduced to pluralities of switches of corresponding digital significance to provide for the conductivity of an individual one of the switches in each pair in accordance with the digital value represented by such signals. A plurality of conductive output members to provide paths through a matrix relationship of the switches and through the output members to one of two output lines. This matrix provides for progressive increases in the number of the output members connected to a particular one of the output lines with progressive increases in the digital value and for a continued connection to the particular output line of output members previously connected to the particular output line with such progressive increases in the digital value. The cumulative current through the particular output line is indicative of the analog value.