Patents Assigned to Bull Information Systems Inc.
  • Patent number: 6480973
    Abstract: In a NUMA architecture, processors in the same CPU module with a processor opening a spin gate tend to have preferential access to a spin gate in memory when attempting to close the spin gate. This “unfair” memory access to the desired spin gate can result in starvation of processors from other CPU modules. This problem is solved by “balking” or delaying a specified period of time before attempting to close a spin gate whenever either one of the processors in the same CPU module just opened the desired spin gate, or when a processor in another CPU module is spinning trying to close the spin gate. Each processor detects when it is spinning on a spin gate. It then transmits that information to the processors in other CPU modules, allowing them to balk when opening spin gates.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: November 12, 2002
    Assignee: Bull Information Systems Inc.
    Inventors: William A. Shelly, David A. Egolf, Wayne R. Buzby
  • Patent number: 5701426
    Abstract: A data processing system which employs a cache memory feature and a method for lowering the cache miss ratio for called operands in the data processing system are disclosed. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement patterns thereamong. Any detected pattern is then employed to predict a succeeding cache miss by prefetching from main memory the signal identified by the predictive address. The apparatus for performing this task is preferably hard wired for speed purposes and includes subtraction circuits for evaluating variously displaced addresses in the miss stack and comparator circuits for determining if the outputs from at least two subtraction circuits are the same indicating a pattern yielding information which can be combined with an address in the stack to develop a predictive address.
    Type: Grant
    Filed: March 31, 1995
    Date of Patent: December 23, 1997
    Assignee: Bull Information Systems Inc.
    Inventor: Charles P. Ryan
  • Patent number: 5263034
    Abstract: In order to provide efficient error detection in a central processor's Basic Processing Unit (BPU) including an AX (address and execution) module, a DN (decimal numeric) module and an FP (floating point) module, each module is provided redundantly in a master/slave pair, and the local result of data manipulation operations performed in each pair are compared for identity before the results are validated for subsequent use in the central processor.
    Type: Grant
    Filed: October 9, 1990
    Date of Patent: November 16, 1993
    Assignee: Bull Information Systems Inc.
    Inventors: Russell W. Guenthner, Clinton B. Eckard, Leonard Rabins, William A. Shelly, Ronald E. Lange, David S. Edwards, Bruce E. Flocken