Abstract: A CMOS output circuit including a differential error amplifier (3) is operated to provide a stable quiescent bias current in an output MOSFET by causing a first current equal to a threshold voltage of a P-channel reference MOSFET (M1) divided by the resistance of a reference resistor (R1) to flow through an N-channel current mirror control MOSFET (M4). A first N-channel current mirror output MOSFET (M6) having a gate coupled to the gate of the N-channel current mirror control MOSFET (M4) and a drain coupled to a drain of the P-channel reference MOSFET (M1) causes a second current proportional to the first current to flow through the P-channel reference MOSFET (M1). The first current is controlled in response to feedback from the P-channel reference MOSFET (M1). A bias current in an error amplifier (3) is controlled in response to the N-channel current mirror control MOSFET (M4).

Abstract: A waveform shaping circuit for use in a function circuit is provided which minimizes interference with a feedback circuit of the function circuit and a load. The waveform shaping circuit disposed in the function circuit includes a voltage transfer unit and a voltage-to-current converter unit. The voltage transfer unit transfers a voltage at an output terminal of an operational amplifier to the converter unit in an electrically isolated condition. The converter unit has a predetermined threshold for the magnitude of the voltage at the output terminal. The converter unit supplies an inverting input terminal of the operational amplifier with a current having a magnitude depending on a relationship in magnitude between the voltage at the output terminal and the predetermined threshold. In one embodiment of the invention the waveform shaping circuit is used to prevent the onset of instability in a high order delta sigma modulator.

Abstract: An operational amplifier output circuit having a low, stable quiescent current includes an input stage (22) receiving an input voltage (v.sub.in ") and producing first (v.sub.1) and second (v.sub.2) signals. An output stage (23) includes a pull-up transistor (1) and a pull-down transistor (2), a base of the pull-up transistor (1) receiving the first signal (v.sub.1). An emitter of the pull-up transistor (1) is coupled by an output conductor (30) to a collector of the pull-down transistor (2). A base of the pull-down transistor is coupled to receive the second signal (v.sub.2), and an emitter of the pull-down transistor (2) is coupled to a second reference voltage conductor (GND). A feedback stage (24) includes a first sensing circuit (36) coupled to the pull-up transistor 1 and produces a third signal (v.sub.3) representing a collector current of the pull-up transistor (1), a second sensing circuit (37) coupled to the pull-down transistor (2) and producing a fourth signal (v.sub.

Abstract: A digital-to-analog converter includes an input circuit (9) producing a plurality of corresponding switch control signals (25) in response to a digital input signal (D.sub.IN) and a resistive ladder network (10A) including an R/2R MSB ladder section (2) including a plurality of "R" resistors (17) and a plurality of "2R" resistors (5), and an R/2R LSB ladder section (3) including a plurality of "R" resistors (17) and a plurality of "2R" resistors (5). A scaling resistor (21) is coupled between a least significant node conductor (7-3) of the MSB ladder section and a most significant node conductor (7-4) of the LSB ladder section. A plurality of switch circuits (6) each selectively conducts a respective parallel resistor circuit (5) to a first reference voltage conductor (VREFH) or a second reference voltage conductor (VREFL) in response to the various switch control signals (25).

Abstract: A circuit provides at least partial thermal shutdown of an integrated circuit chip including a functional circuit (7) in response to detection of a hot spot in a first area of the chip. First (Q1) and second (Q3) transistors in a second area (3) of the chip are located a first distance (10) from the second area of the chip, and third (Q4) and fourth (Q2) transistors in a third area (4) of the chip are located a second distance (11) substantially greater than the first distance from the first area. The functional circuit (7) dissipates power in the first area, causing a temperature in the hot spot to rise to approximately a first temperature T3 and causing the temperature of the first and second transistors to be a second temperature T2 and causing the temperature of the third and fourth transistors to be a third temperature T1.

Abstract: A push-pull output stage includes an NPN pull-up transistor (Q6) and an NPN pull-down transistor (Q7) connected to an output. A compensation capacitor 17 is coupled between the collector and base of the pull-down transistor. A differential input stage includes emitter-coupled first (Q2) and second (Q3) NPN input transistors each coupled by a degeneration resistor to a constant current source. A base of the first NPN input transistor (Q2) is coupled to receive a shifted input voltage (V.sub.IN), and a base of the second NPN input transistor is coupled to the output conductor (3). The collectors of the first (Q2) and second (Q3) input transistors are connected to the sources of a folded cascode circuit including first (J1) and second (J2) cascode P-channel JFETs, respectively, the drains of which are connected to a current mirror output transistor (Q5) and a current mirror control transistor (Q4), respectively.

Abstract: A three-stage amplifier including first, second, and third sequentially coupled stages is compensated without use of compensation capacitors, by applying an input signal to an input of the first stage and a first input of a first feed-forward stage, coupling an output signal of the first feed-forward stage to an output of the second stage, the second stage having an input coupled to an output of the first stage, coupling an output signal of the first stage to an input of a second feed-forward stage, coupling an output of the second feed-forward stage to an output of the third stage, coupling the input signal to an input of a third feed-forward stage, and coupling an output of the third feed-forward stage to the output of the third stage.

Abstract: Power control circuitry is provided in an analog-to-digital converter (1) having a CDAC array (2) coupled to an analog input signal, a comparator (3), and a successive approximation register circuit (5). The power control circuitry includes a bias control circuit (4) responsive to a powerdown signal and associated wakeup signal to produce a bias control signal (V.sub.BIAS). The bias control circuit includes a controllable current mirror circuit (10) which produces a first voltage (V.sub.C) on a first conductor (13) when the powerdown signal is at a first level to allow operation of the comparator in conjunction with the CDAC array and the successive approximation register circuit. The bias control circuit also includes a wakeup circuit (20) which precharges the first conductor (13) to a predetermined bias voltage (V.sub.C ') that is close in value to the first voltage (V.sub.C) in response to occurrence of the first level of the powerdown signal. The bias control signal V.sub.

Abstract: A programmable integrated circuit capacitor array includes a plurality of binarily weighted capacitors (16) and a plurality of switches (18) selectively coupling the capacitors in parallel between first and second terminals. A control circuit (10) responds to a plurality of capacitance selection inputs (CS0,1,2) in conjunction with a plurality of trim inputs (TR0,1) and a sign input (TRS) to produce a plurality of selection signals (SEL0,1 . . . 7) on control electrodes of the switches to couple one or more of the capacitors and thereby provide an accurate value of the desired capacitance between the first and second terminals despite any manufacturing deviations in capacitance per unit area.

Abstract: An integrated circuit resistor array suitable for use as resistors included in a high performance analog integrated circuit is provided. A plurality of resistor stripes are collectively arranged in a region on a substrate. The resistor stripes are made of the same material and designed to have the same cross-sectional area. The resistor stripes are electrically connected through first metal layer conductors. Second metal layer conductors connect the stripes to external circuits. Different resistors have matched voltage dependencies.

Abstract: The voltage swing on an output conductor of a high speed, high dynamic range regulated cascode current mirror is increased by providing a first transistor (M1) of a first conductivity type having a source electrode coupled to a first reference voltage conductor (GND), a gate electrode coupled to a first bias voltage circuit (M5,I1), and a drain coupled to a first conductor (4), a second transistor (M2) of the first conductivity type having a source electrode coupled to the first conductor (4), a gate electrode coupled to a second conductor (3), and a drain electrode coupled to the output conductor (2), and a third transistor (M3) of the first conductivity type having a source electrode coupled to the first reference voltage conductor (GND) and a drain coupled to the second conductor (3). A load circuit (I.sub.2) is coupled between a second reference voltage conductor (V.sub.DD) and the second conductor (3), wherein the third transistor (M3) and the load circuit (I.sub.

Abstract: A logarithmic attenuator circuit includes a resistive attenuator in which the series resistors are P-channel MOSFETs with gate electrodes connected to V.sub.DD and the parallel resistors are P-channel MOSFETs which also function as switches. A control circuit (8B) produces a plurality of successive control signals (V1,2 . . . 10) on the gate electrodes of the successive MOSFETs which functions as switches in response to a gain control signal (V.sub.

Abstract: A digital-to-analog converter is provided which compensates for relative errors among weighting elements used for D/A conversion. The converter includes a decoder, a rotator, and a weighting section. The rotator receives decoded signals from a decoder to produce rotated output signals for activating or deactivating a plurality of weighting elements, respectively, included in the weighting section. The rotated output signals assure that the same number of weighting elements are activated in each of a plurality of sub-periods of time constituting a main period of time of the D/A conversion and that each of the plurality of weighting elements is activated the same number of times during the whole main period.

Abstract: A CMOS output circuit including a differential error amplifier (3) is operated to provide a stable quiescent bias current in an output MOSFET by causing a first current equal to a threshold voltage of a P-channel reference MOSFET (M1) divided by the resistance of a reference resistor (R1) to flow through an N-channel current mirror control MOSFET (M4). A first N-channel current mirror output MOSFET (M6) having a gate coupled to the gate of the N-channel current mirror control MOSFET (M4) and a drain coupled to a drain of the P-channel reference MOSFET (M1) causes a second current proportional to the first current to flow through the P-channel reference MOSFET (M1). The first current is controlled in response to feedback from the P-channel reference MOSFET (M1). A bias current in an error amplifier (3) is controlled in response to the N-channel current mirror control MOSFET (M4).

Abstract: An operational amplifier circuit includes a differential operational amplifier and a common mode feedback circuit with first and second transistors (16 and 20) having source electrodes connected to first and second supply voltage conductors and drains coupled to first and second outputs of the operational amplifier, respectively. First and second capacitors (24 and 25) are connected in series between gate electrodes of the first and second transistors and have a common point connected to the first output. A first switch capacitor circuit periodically refreshes the first capacitor to a voltage equal to the average of the first and second supply conductor voltages minus first and second predetermined bias voltages, respectively. A second similar common mode feedback circuit is coupled to the second output a differential output voltage produced by the operational amplifier results in equal excursions of the first and second outputs on opposite sides of the common mode feedback signal.

Abstract: An integrating circuit includes an operational amplifier and an integrating capacitor which is decoupled from the output of the operational amplifier and precharged to a positive reference voltage before each integration cycle. During each integration cycle the operational amplifier output decreases from the reference voltage toward but not below ground. This allows the operational amplifier to be included as a front-end integrator to a delta-sigma analog-to-digital converter that is powered only by a single power supply. In the described embodiment, the output is coupled to an input of an auto-zeroing stage which provides negative feedback to stabilize the operational amplifier when the integrating capacitor is disconnected during precharging and a bandwidth control input which couples a larger compensation capacitance to reduce the bandwidth during integration to reduce RMS noise.

Abstract: A characteristic tone in a delta-sigma analog-to-digital converter is shifted out of an audible pass band without diminishing dynamic range or signal-to-noise ratio thereof by operating the digital-to-analog converter to measure its offset voltage. If the amplitude of the measured offset voltage exceeds a predetermined value, no dither signal is applied to the input of the delta-sigma modulator. If the measured offset voltage is less than the predetermined value, a positive DC dither voltage is added to the input voltage of the delta-sigma modulator if the measured offset voltage is positive, or is subtracted if the measured offset voltage is negative.

Abstract: An apparatus and method for generating signals. According to one embodiment, the apparatus has an oscillator generating a series of signals, an output stage for transforming the series of signals into a second series of signals, and a watchdog for providing a control signal to the output stage to hold the output stage in a selected state and for changing the control signal to enable the output stage in the selected state when the oscillator generates a first signal of the series of signals.

Abstract: A DC to DC converter repeatedly divides a first digital signal (26) into 8 time frames, and repeatedly generates a second digital signal (V.sub.S) during one of the 8 time frames. A DC input signal (V.sub.IN) is converted to a pulse width modulated signal (PWM) representative of the DC input signal, which is amplified and applied across a primary winding (4A) of an isolation transformer (4) during the one time frame. A second pulse width modulated signal produced across a secondary winding (4B) of the isolation transformer is rectified to produce a DC output voltage, which is compared to a reference voltage to produce a error signal. The error signal is transmitted across the isolation transformer during the one time frame and is used to adjust the pulse width modulating, to thereby regulate the DC output voltage.

Abstract: Differential filters for removing both normal-mode and common-mode noises are provided. A first-order differential low pass filter is composed of a first resistor connected between a first input terminal and a first output terminal, a second resistor having the same resistance value as the first resistor and connected between a second input terminal and a second output terminal, a first capacitor connected between the first output terminal and a reference potential, a second capacitor having the same capacitance value as the first capacitor and connected between the second output terminal and the reference potential, and a third capacitor connected between the first output terminal and the second output terminal.