Abstract: A precision voltage level shift circuit includes an emitter follower input circuit including a lateral PNP transistor having a base receiving an input voltage, and an emitter coupled to both an output terminal and a first current source. JFET is coupled between a collector of the input transistor and a first supply voltage conductor. A second PNP transistor has a base coupled to the collector of the first transistor and an emitter coupled to a second current source. A differential amplifier has a first input coupled to the output terminal, a second input coupled to the emitter of the second transistor, and an output coupled to the load element. The differential amplifier operates to maintain the voltage drop across the JFET at a level such that the emitter of the second PNP transistor is equal to the voltage of the emitter of the lateral PNP transistor to thereby maintain the collector-emitter voltage thereof at a constant value.

Abstract: A compensated bias current circuit for use in an operational amplifier including a differential input stage, a gain stage, and an output driver stage. The compensated bias current circuit includes a PNP current mirror control transistor having an emitter coupled to a first supply voltage conductor, a collector coupled by a first conductor to a first terminal of a current source circuit, and a base connected to a second conductor, with the second conductor connected to first and second PNP current mirror output transistors in the gain stage and a third PNP current mirror output transistor in the output driver stage.

Abstract: A transformer. According to one embodiment, the planar transformer has a first winding, a first conducting surface adjacent to the first winding, a second winding and a second conducting surface adjacent to the second winding. The first conducting surface is coupled to a first ground and the second conducting surface is coupled to a second ground.

Abstract: An integrated circuit photodetector includes a transimpedance amplifier including a differential amplifier stage with PNP emitter-coupled transistors and a PNP input transistor which are biased only by base currents of the emitter-coupled transistors, to achieve low input bias current. Low noise operation is achieved by bypass capacitors coupled between the bases and emitters of the input transistors, respectively. A constant current source supplies a current which develops a small pedestal voltage across a resistor to bias the non-inverting input of the transimpedance amplifier so as to avoid nonlinear amplification of low level light signals. A positively biased N-type guard tub surrounds the photodetector, which is formed in a junction-isolated N region on a P substrate, to collect electrons generated in the substrate by deep-penetrating IR light to prevent them from causing amplification errors.

Abstract: A circuit and method for reducing an input bias current flowing from an external signal source coupled to an input terminal of the circuit, the circuit being coupled to an input device having a device leakage current related to a device voltage. According to a preferred embodiment, a replica voltage source provides a replica voltage equal to the device voltage. A cancellation device is coupled to the replica voltage source so that the replica voltage is applied to the cancellation device. The cancellation device is further coupled to the input terminal for providing a cancellation current equal to the device leakage current, wherein the input bias current is equal to the difference between the device leakage current and the cancellation current.

Abstract: A push-pull output circuit includes first and second transistors each having a base coupled to a first conductor coupled to respond to an input signal. An emitter of the first transistor is coupled by a first resistor to a first supply voltage conductor and an emitter of the second transistor is coupled to the first supply voltage conductor. A pull-up circuit is coupled to the collectors of the first and second transistors. An output conductor is coupled to the collector of the second transistor. A third transistor having an emitter connected to the collector of the first transistor and a base and collector of a fourth transistor. A bias current source is coupled to the base of the third and fourth transistors to maintain the collector of the first transistor and the output conductor at substantially equal voltages.

Abstract: A method and apparatus for protecting a DC-AC converter having a transformer. According to one embodiment, an oscillator generates a periodic signal having a frequency. A switch switches an input voltage across a first winding of the transformer in accordance with the periodic signal. A watchdog device disables the switch if the frequency falls below a threshold frequency.

Abstract: A switched capacitor input sampling circuit in a chopper stabilized delta sigma modulator includes first and second input terminals adapted to receive a differential analog input voltage therebetween and first and second terminals coupled to first and second charge summing conductors, respectively, of the delta sigma modulator.

Abstract: An inverter device is provided which comprises an inverter including a pair of transistors, and first and second delay circuits. The first and second delay circuits are connected to respective inputs of the pair of transistors so as to cause the transistors of the pair to switch with a greater time difference, thereby reducing noise due to switching operations in the inverter.

Abstract: Programmable resolution/bias current control circuitry is provided in a delta sigma analog-to-digital converter including an input sampling circuit, a feedback reference sampling circuit, an integrator including an operational amplifier, a comparator, and a digital filter, the input sampling circuit and the feedback reference sampling circuit being coupled to a first input of the operational amplifier, an output of the operational amplifier being coupled to an input of the comparator, an output of the comparator being coupled to an input of the digital filter. The programmable resolution/bias control circuitry includes a clock generator circuit supplying a clock signal to the input sampling circuit and the feedback sampling circuit at a sampling frequency determined by a sampling frequency control signal. A bias current generator circuit supplies a bias current to the operational amplifier to control the settling time of an output step voltage signal produced by the operational amplifier.

Abstract: An oversampling digital-to-analog converter is provided with an auto-muting circuit which reduces noise in an analog output signal when a digital input signal remains at zero. Auto-muting circuit includes an input reference level code detection section which detects an input reference level code in the digital input signal. An output reference level code in a modulated output generated from an oversampling modulator is detected by an output reference level code detection section provided in the auto-muting circuit. A modulated output alteration section is provided which operates in response to the result of the detections to selectively pass the modulated output without any alteration or alter the modulated output by substituting it with output reference level codes.

Abstract: A compensation circuit in a high speed integrated circuit operational amplifier that includes an input stage having first and second outputs connected to emitters of first and second PNP cascode transistors. A base of an NPN cascode transistor is coupled to a collector of the first PNP cascode transistor. A resistor circuit is connected between the collectors of the second PNP cascode transistor and the NPN cascode transistor. First and second inputs of a diamond follower output buffer are connected to the collectors of the NPN cascode transistor and second PNP cascode transistor, respectively. A compensation circuit includes first and second compensation capacitors connected to the collectors of the NPN cascode transistor and the second PNP cascode transistor, respectively, to prevent instability of an output voltage of the diamond follower buffer circuit.

Abstract: A high speed integrated circuit operational amplifier chip having first, second, third and fourth successive edges includes a thermal centerline parallel to the second and fourth edges. An output driver circuit is located adjacent to an output bonding pad along the third edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced differential heating of the operational amplifier chip relative to the thermal centerline. A low gain differential input circuit is located adjacent to the first edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced responses of matched transistors in the low gain differential input circuit to isotherms produced by the differential heating.

Abstract: A high speed integrated circuit operational amplifier chip first, second, third and fourth successive edges includes a thermal centerline parallel to the second and fourth edges. An output driver circuit is located adjacent to an output bonding pad along the third edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced differential heating of the operational amplifier chip relative to the thermal centerline. A differential input circuit is located adjacent to the first edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced responses of matched transistors in the low gain differential input circuit to isotherms produced by the differential heating. The most thermally sensitive transistors are disposed along or symmetrically about the thermal centerline to provide approximately balanced response by such transistors to differential heating by the output driver circuit.

Abstract: A compensation circuit in a high speed integrated circuit operational amplifier that includes an input stage having first and second outputs connected to emitters of first and second PNP cascode transistors. A base of an cascode transistor is coupled to a collector of the first PNP cascode transistor. A resistor circuit is connected between the collectors of the second PNP cascode transistor and the NPN cascode transistor. First and second inputs of a diamond follower output buffer are connected to the collectors of the NPN cascode transistor and second PNP cascode transistor, respectively. A compensation circuit includes first and second compensation capacitors connected to the collectors of the NPN cascode transistor and the second PNP cascode transistor, respectively, to prevent instability of an output voltage of the diamond follower buffer circuit.

Abstract: A planar transformer assembly includes an insulative layer, a first spiral winding thereon circumscribing a magnetic flux path, a second spiral winding thereon in non-overlapping relation to the first spiral winding circumscribing the magnetic flux path, and a ferrite core assembly including first and second core sections defining a shallow gap or passage within which the spiral windings are disposed. In one embodiment, a plurality of laminated insulative layers are provided with a primary winding including a plurality of series-connected spiral subwindings and a non-overlapping secondary winding formed on the various insulative layers. The non-overlapping structure and the order of the various windings minimize electric field gradients and thereby minimize electric field coupled noise currents.

Abstract: An integrated circuit photodetector includes a transimpedance amplifier including a differential amplifier stage with PNP emitter-coupled transistors and a PNP input transistor which are biased only by base currents of the emitter-coupled transistors, to achieve low input bias current. Low noise operation is achieved by bypass capacitors coupled between the bases and emitters of the input transistors, respectively. A constant current source supplies a current which develops a small pedestal voltage across a resistor to bias the non-inverting input of the transimpedance amplifier so as to avoid nonlinear amplification of low level light signals. A positively biased N-type guard tub surrounds the photodetector, which is formed in a junction-isolated N region on a P substrate, to collect electrons generated in the substrate by deep-penetrating IR light to prevent them from causing amplification errors.

Abstract: A conversion circuit digitizes first and second differential analog signals conducted by first and second conductors for digital processing in a motor control system. The conversion circuit includes an analog-to-digital conversion circuit. The analog-to-digital conversion circuit includes a CDAC having a charge summing conductor connected to an input of a bit decision comparator and first and second simultaneously sampled differential sample and hold MSB circuits connected to the charge summing conductor. The first and second differential analog signals are simultaneously sampled and held in the first and second differential sample and hold MSB circuits, respectively, and then are sequentially converted to digital numbers by the analog-to-digital conversion circuit.

Abstract: An electronically controllable low capacitance active bus line terminator achieves low output terminal capacitances by connecting emitters of switch transistors directly to the output terminals. Termination resistors are connected directly between an output of a voltage regulator circuit and collectors of the switch transistors. Emitters of optional clamp transistors can be connected to bases or collectors of the switch transistors to limit or prevent "ringing" of bus conductors connected to the output terminals if the switch transistors are turned on. The bus conductors are thereby isolated from parasitic capacitances associated with the termination resistors and the collectors of the switch transistors when they are turned off.

Abstract: A current integrating analog-to-digital converter includes a comparator having a non-inverting input coupled to receive a ground voltage and an inverting input coupled to an input conductor, with an input current flowing through the input conductor, an integrating capacitor having a first terminal coupled by an isolation switch to the input conductor. A reset circuit is coupled to the integrating capacitor and is operative to reset the integrating capacitor before each integrating cycle. A digital-to-analog converter, which may be a CDAC, has an output coupled to a second terminal of the integrating capacitor, which may constitute the capacitors of the CDAC. An input of a tracking circuit is coupled to an output of the comparator to produce digital signals on digital inputs of the digital-to-analog converter to maintain the input of the comparator close to a virtual ground voltage, a digital signal on the inputs of the digital-to-analog converter representing the integral of the input current.