Abstract: Methods and devices are described, including a near-field communications (NFC) or radio frequency identification (RFID) device comprising an NFC or RFID circuit, an antenna having at least a first terminal, a first rectifier connected to the first terminal of the antenna, a switch between the first rectifier and the NFC or RFID circuit, a voltage detector for detecting a voltage in the device caused by a signal received at the antenna, and a control module for controlling the switch, wherein when the voltage exceeds a threshold magnitude, the control module controls the switch to be in an open state and, after a predetermined time period, determines whether the voltage still exceeds the threshold magnitude and, if the voltage still exceeds the predetermined magnitude, controls the switch to be in the open state.

Abstract: A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and transistors.

Abstract: A design for an improved metal-on-metal capacitor design is described. The design includes a substantially diagonal feedline (411, 412, 413) in each metal layer. Each metal layer (21, 22, 23) comprises two sets of metal fingers which are interleaved. Each set of fingers comprises two subsets of fingers and the subsets of fingers are arranged at right angles to each other. Fingers in a first of the two sets are all connected to the diagonal feedline, while fingers in the other set are connected together via fingers at the periphery of the device. The design is repeated in adjacent layers, where the design may be identical or rotated (e.g by 180°) between adjacent metal layers.

Abstract: An improved wafer level chip scale packaging technique is described which does not use an encapsulated via to connect between a redirection layer and a pad within the pad ring on the semiconductor die. In an embodiment, a first dielectric layer is formed such that it terminates on each die within the die's pad ring. Tracks are then formed in a conductive layer which contact one of the pads and run over the edge of an opening onto the surface of the first dielectric layer. These tracks may be used to form an electrical connection between the pad and a solder ball.

Abstract: An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source terminal or a drain terminal. The source and the drain terminal are arranged orthogonally to the local interconnect lines and each terminal is significantly wider than a local interconnect line. In an example, the local interconnect lines are formed in a first metal layer and the source and drain terminals are formed in one or more subsequent metal layers.

Abstract: A frequency shifter configured to shift the frequency of a signal, the frequency shifter comprising: a resonant structure configured to mechanically resonate at a first frequency; and a plurality of capacitors, each capacitor having a variable plate separation distance, wherein the resonant structure is configured to cause the plate separation distance of each capacitor to oscillate so as to cause the frequency of the signal to shift by the first frequency.

Abstract: A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and transistors.

Abstract: The present invention provides a locked loop circuit in which the input clock signal is delayed according to a saw-tooth signal in order to output a range of frequencies not necessarily equal to an integer multiple of the input clock signal. The absolute value of the delay (i.e. the difference between the maximum and minimum values of the saw-tooth delay) can be calibrated by detecting the value of the circuit phase detector at the wrap point of the saw-tooth.

Abstract: An improved die seal ring is described which includes at least one break. In the region of the break in the die seal ring, the doping is modified so that the impedance of the electrical path across the break through the substrate is increased. Offsets in the break may also be used and the offset may be within a break in a track and/or between breaks in different tracks, where the die seal ring includes more than one track.

Abstract: An improved wafer level chip scale packaging technique is described which does not use an encapsulated via to connect between a redirection layer and a pad within the pad ring on the semiconductor die. In an embodiment, a first dielectric layer is formed such that it terminates on each die within the die's pad ring. Tracks are then formed in a conductive layer which contact one of the pads and run over the edge of an opening onto the surface of the first dielectric layer. These tracks may be used to form an electrical connection between the pad and a solder ball.

Abstract: A co-existence method is described. The method comprises setting a priority level of a slot based on the likelihood that the slot will be required by a first radio and signaling the priority level to radio which is co-located with the first radio and which shares a resource with the first radio. The slot may, for example, be a re-transmission slot following a primary transmission slot or may be a sniff anchor point. The likelihood may be determined based on one or more factors, such as historical data or knowledge of the activity of a peer of the first radio.

Abstract: An improved wafer level chip scale packaging technique is described which does not use an encapsulated via to connect between a redirection layer and a pad within the pad ring on the semiconductor die. In an embodiment, a first dielectric layer is formed such that it terminates on each die within the die's pad ring. Tracks are then formed in a conductive layer which contact one of the pads and run over the edge of an opening onto the surface of the first dielectric layer. These tracks may be used to form an electrical connection between the pad and a solder ball.

Abstract: A receiver comprising: an antenna for receiving signals in a plurality of frequency bands; an integrated circuit including a plurality of amplifiers, wherein each of the plurality of amplifiers is configured to amplify signals in one of the plurality of frequency bands; and a plurality of selectable receive paths, each of the plurality of selectable receive paths connecting an output of the antenna to an input of one of the plurality of amplifiers and including a resonant circuit.

Abstract: A global positioning satellite (GPS) receiver that includes a radio frequency (RF) receiver receiving a first GPS signal from a GPS satellite and a processor. The processor is configured to correlate the first GPS signal with a plurality of reference signals to produce a plurality of correlations, detect a transition between receiving the first GPS signal and receiving a second GPS signal from the GPS satellite based on a phase shift in the correlations, and if the transition is detected, compensate for the phase shift when computing a range to the GPS satellite.

Abstract: A receiver for a telecommunications system, wherein the receiver is capable of using a plurality of available alternative receiver sub-systems and the receiver comprises selection means for selecting one of the plurality of receiver sub-systems for use in processing a received signal according to conditions of the propagation channel through which the received signal was received.

Abstract: Methods of encoding a signal using a perceptual model are described in which a signal to mask ratio parameter within the perceptual model is tuned. The signal to mask ratio parameter is tuned based on a function of the bitrate of the part of the signal which has already been encoded and the target bitrate for the encoding process. The tuned signal to mask ratio parameter is used to compute a masking threshold for the signal which is then used to quantize the signal.

Abstract: An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source terminal or a drain terminal. The source and the drain terminal are arranged orthogonally to the local interconnect lines and each terminal is significantly wider than a local interconnect line. In an example, the local interconnect lines are formed in a first metal layer and the source and drain terminals are formed in one or more subsequent metal layers.

Abstract: The present system relates to a GNSS receiver that includes a processor. The processor is configured to receive a temperature signal from a temperature sensor indicating an operating temperature of an resonator. The processor is also configured to compute a frequency and a frequency correction data of the resonator based on the temperature and a frequency model of the resonator. The processor then transmits the frequency correction data to an RF receiver which utilizes the frequency correction data and the resonator to receive and RF signal.

Abstract: A method and system for sharing access to a storage device. Two processing devices are connected to a storage device interface. The processing devices are interconnected to allow communication with regard to access to the storage device interface. Access to the storage device interface is controlled by the first and second processing devices exchanging signals. Embodiments of the invention may be a mobile device configured to play audio files from a memory card connected to the mobile device. A communications link may be established to a remote device for the transfer of data between devices.

Abstract: The present invention is related to location positioning systems, and more particularly, to a method and apparatus for making accuracy improvements to a GPS receiver's navigation calculations. According to a first aspect, the invention includes maintaining a table of height attributes for major cities and urban areas around the world (contour table) in the GNSS chipset. The information in the table preferably includes latitude, longitude of the city along with height attributes of those cities, such as the average, min, max height and region boundary etc. Additional information such as average gradient could also be saved in the table. According to further aspects, when GPS signals are degraded in environments such as urban canyons, the height information can be obtained from the table and used to improve the navigation solution.