Abstract: Provided is an array substrate. The array substrate includes a base substrate, a gate line, a data line, a discharge line, a first pixel electrode, a first thin film transistor, a second thin film transistor and a first connection line. A control electrode of the first thin film transistor and a control electrode of the second thin film transistor are both connected to the gate line. The first electrode of the first thin film transistor is connected to the data line. Both the second electrode of the first thin film transistor and the first electrode of the second thin film transistor are connected to the first pixel electrode by the first connection line. The second electrode of the second thin film transistor is connected to the discharge line.

Abstract: The present application provides an array substrate and a display panel. The array substrate includes a gate of a thin film transistor; a first electrode of the transistor, including a first body and a first end; a second electrode of the transistor, including a second body and a second end; orthographic projections of the first body and the second body being located in an orthographic projection of the gate, orthographic projections of at least partial area of the first end and at least partial area of the second end not overlapping with the orthographic projection of the gate, an orthographic projections of the first end and the second end being both located on the same side of the orthographic projection of the gate; in a first direction, an average distance from the first end to the second end is greater than that from the first body to the second body.

Abstract: Provided is a liquid crystal display panel. The liquid crystal display panel includes: a first substrate and a second substrate that are opposite to each other, and a liquid crystal layer between the first substrate and the second substrate. The liquid crystal display panel includes a plurality of sub-pixel regions. Each of the plurality of sub-pixel regions includes 4N sub-pixel sub-regions arranged in a single column, and the 4N sub-pixel sub-regions are organized into one group, or a plurality of groups that are adjacent to each other. A same group of sub-pixel sub-regions includes two first sub-regions and two second sub-regions. N is an integer greater than or equal to 1.

Abstract: An array substrate and a display device are provided. The array substrate includes a base substrate, gate lines and a metal layer on the base substrate. The metal layer is located on a side of the gate lines away from the base substrate, and includes data lines, a first connecting portion and a first electrode and a second electrode of a thin film transistor. The first electrode is electrically connected to a pixel electrode by the first connecting portion. A gate line includes a gate line pad which includes a protrusion protruding towards a pixel region relative to the portion of the gate line other than the gate line pad. The metal layer located in the pixel region includes a plurality of traces extending along at least part of a contour of the pixel region and including first traces surrounding the protrusion.

Abstract: Provided is an array substrate. The array substrate includes a base substrate, a gate line, a data line, a discharge line, a first pixel electrode, a first thin film transistor, a second thin film transistor and a first connection line. A control electrode of the first thin film transistor and a control electrode of the second thin film transistor are both connected to the gate line. The first electrode of the first thin film transistor is connected to the data line. Both the second electrode of the first thin film transistor and the first electrode of the second thin film transistor are connected to the first pixel electrode by the first connection line. The second electrode of the second thin film transistor is connected to the discharge line.

Abstract: A driving circuit and a display device are provided. The driving circuit includes a pull-up node, an input module, a pull-up module, a first output module and a second output module; the input module is electrically connected to an input terminal and a pull-up node, and is configured to control a potential of the pull-up node under the control of an input signal provided by the input terminal; the pull-up module controls the potential of the pull-up node; the first output module outputs a first gate driving signal through the first driving output terminal under the control of the potential of the pull-up node; the second output module outputs a second gate driving signal through the second driving output terminal under the control of the potential of the pull-up node. The present disclosure may output a plurality of stages of gate driving signals and reduce the number of transistors, which is facilitate to the narrow border.

Abstract: The present disclosure provides a pixel unit, a display substrate, a display panel, and a display device. The pixel unit includes a slit electrode having a slit. The pixel unit includes at least two sub-pixels corresponding to different colors, each of the pixels includes n domain areas arranged along a first direction, n is a positive integer greater than or equal to 2, extension directions of the slits of the slit electrodes in any two adjacent domain areas in the n domain areas of the pixel unit are different, an acute angle between an extension direction of the slit in each domain area and a second direction is a predetermined angle, the predetermined angle is greater than or equal to 30° and less than 45°, and the second direction intersects with the first direction.

Abstract: The present disclosure provides a display panel, a manufacturing method and a display device. The display panel includes a first substrate, a second substrate and liquid crystal molecules. Each sub-pixel includes n domains, and at least two of the n domains are arranged in a first direction. An alignment film is arranged on one or both of the first substrate and the second substrate and provided with alignment directions, and/or slit electrodes each with a slit are arranged on one or both of the first substrate and the second substrate. The alignment directions in at least two adjacent domains in the n domains are different and/or extension directions of the slits in any two adjacent domains are different, so that the liquid crystal molecules in different domains are provided with different pretilt angles.

Abstract: An array base plate includes a substrate base plate; a repairing line and data lines provided on one side of the substrate base plate, wherein the data lines include a first data line, the first data line has a first breaking point, and first data lines located on two sides of the first breaking point are individually connected to the repairing line; a first insulating layer provided on one side of the repairing line and the data lines that is opposite to the substrate base plate; and pixel electrodes provided on one side of the first insulating layer that is opposite to the substrate base plate, wherein the pixel electrodes include a first pixel electrode; the first data line is connected to the first pixel electrode; and orthographic projections on the substrate base plate of the repairing line and the first pixel electrode intersect or overlap.

Abstract: Provided is a curved liquid crystal display panel, including a color film substrate and an array substrate. An orthographic projection of the color film substrate on the array substrate is within the array substrate. The color film substrate includes a first side surface and a second side surface. The array substrate includes a third side surface and a fourth side surface. The first side surface is adjacent to and staggered from the third side surface. The second side surface is adjacent to and staggered from the fourth side surface. At positions where the third side surface and the fourth side surface are disposed, each of a side, proximal to the color film substrate, of the array substrate and a side, distal from the color film substrate, of the array substrate includes a structure formed by a grinding process.

Abstract: The present disclosure provides a display substrate, a method for manufacturing the same, and a display device, which belongs to the technical field of displays. The display substrate includes: a first signal line, located on a base substrate and extending in a first direction; a second signal line, located on the base substrate and extending in a second direction, where the second signal line is arranged in a different layer from the first signal line, the second direction intersects with the first direction, the first signal line includes a first portion, and a first orthographic projection of the first portion on the base substrate is located within a orthographic projection of the second signal line on the base substrate; the display substrate further includes: an isolation pattern, located on a side of the first signal line away from the base substrate.

Abstract: The present application provides an array substrate and a display panel. The array substrate includes a gate of a thin film transistor; a first electrode of the transistor, including a first body and a first end; a second electrode of the transistor, including a second body and a second end; orthographic projections of the first body and the second body being located in an orthographic projection of the gate, orthographic projections of at least partial area of the first end and at least partial area of the second end not overlapping with the orthographic projection of the gate, an orthographic projections of the first end and the second end being both located on the same side of the orthographic projection of the gate; in a first direction, an average distance from the first end to the second end is greater than that from the first body to the second body.

Abstract: Provided is an array substrate. The array substrate includes a base substrate, a gate line, a data line, a discharge line, a first pixel electrode, a first thin film transistor, a second thin film transistor and a first connection line. A control electrode of the first thin film transistor and a control electrode of the second thin film transistor are both connected to the gate line. The first electrode of the first thin film transistor is connected to the data line. Both the second electrode of the first thin film transistor and the first electrode of the second thin film transistor are connected to the first pixel electrode by the first connection line. The second electrode of the second thin film transistor is connected to the discharge line.