Abstract: A method for automatic hidden node detection that includes observing frame exchange sequences that conform to a MAC standard such as the IEEE 802.11 standard. The method includes detecting a hidden node upon receiving a response frame without previously receiving the frame causing the response. Similar conclusions may be drawn from longer frame sequences. When a hidden node has been detected with reasonable certainty, a hidden node report is sent to a hidden node manager. In one embodiment, the hidden node manager is centralized, and in another, the management function is performed in a distributed manner. Upon receiving a report, the hidden node manager automatically invokes hidden node avoidance measures by sending one or more action frames. In another embodiment, the hidden node manager turns on a hidden node mitigation method. In the case of the IEEE 802.11 standard, the hidden node manager turns on the IEEE 802.11 hidden node mitigation method based on RTS/CTS exchange.

Abstract: An interleaver and interleaving method each includes two stages, and is useful in coded orthogonal frequency division multiplexed (COFDM) wireless local area networks. A first stage performs a first block permutation and a second stage performs bit order permutation to effectuate a second group permutation. A corresponding de-interleaver does just the opposite at the receiver. A double-buffer version includes writing data into one memory block in a first order while reading data from the second block in a second order, with the first and second orders selected to effectuate the first block permutation.

Abstract: A wireless computer data network includes several untethered mobile units that make ad-hoc data connections with an Internet-connected base station using the IEEE-802.11a standard. Each unit includes a radio transceiver fully integrated on a single semiconductor chip. The receiver portion is a double-conversion superheterodyne type, and shares the same intermediate and local oscillator frequencies with a two-stage up-conversion transmitter. Two on-chip synthesizers that each include a voltage-controlled oscillator and phase-locked loop can be operated independently for each conversion stage, or operated in offset mode. External reference frequencies can be injected for voltage-controlled oscillator and phase-locked loop testing, chip characterization, and automatic compensation modeling. Each mobile and base unit can be outfitted with transmit/receive antenna transfer switches, RF-power amplifiers, and low-noise receiver amplifiers to increase operating range.

Abstract: A method and apparatus for estimating channel characteristics in a multicarrier wireless receiver such as an OFDM wireless receiver. The method includes determining a channel estimate for each of a set of subcarriers by receiving multicarrier data as a result of a wireless transmission of data that includes a known signal, wherein the determining uses a part of the received data that corresponds to the known signal. The method further includes smoothing the channel estimates according to a smoothing filter to form smoothed channel estimates. The smoothed channel estimate for a particular subcarrier includes a contribution from the channel estimates of the particular subcarrier's one or more immediate neighbors to take advantage of correlation that may exist between the particular subcarrier's channel and the channels of that subcarrier's one or more immediate neighbors.

Abstract: A method and apparatus for synchronizing a local clock value in a wireless receiver receiving a data unit containing synchronization information. The method includes receiving a first data unit containing synchronization information, extracting the synchronization information from the received first data unit, copying a local free-running clock at a known reference point in time relative to the time the first data unit was received to generate a local timestamp; and calculating an offset to the free-running clock using the extracted synchronization information and the local timestamp, the calculating in non real-time, such that the sum of the calculated offset and the value of the free-running clock provides a local clock value that is approximately synchronized in time. The apparatus implementing the method is part of a node of a wireless station, and provides a time synchronization function, typically at the MAC layer.

Abstract: A digital AGC system for burst operation, particularly suited for receiving packets in a wireless local area network. One embodiment includes a log detector that provides a signal strength measure, called the received signal strength indication (RSSI) over a wide dynamic range. The AGC system includes estimating the power in a received signal by averaging the log of the signal power. The Start of Packet detection avoids using the radio receiver's main analog to digital converters to preserve power.

Abstract: A monolithic transceiver integrated circuit that includes a substrate, a transmitter subsystem of one or more subcircuits on the substrate, and a receiver subsystem of one or more subcircuits on the substrate. Also included is a bias current supply coupled to the receiver and transmitter subsystems to provide bias current. The bias current supply includes a first bias circuit on the substrate coupled to, and to supply bias current to, a first subcircuit of the transmitter subsystem. The first bias circuit includes a first current modulator having a first switch input to indicate that the bias current is to start or stop being supplied to the first subcircuit. The first current modulator is to control the rate of change of supplied bias current in response to the first switch input. The first subcircuit may be a power amplifier. The control of the rate of change reduces oscillator pull in at least one oscillator included in the integrated circuit.

Abstract: A monolithic radio integrated circuit includes a substrate, a set of one or more analog subcircuits on the substrate, a programmable bias current supply on the substrate coupled to the set to provide bias currents to the analog subcircuits of the set including programmable bias currents to one or more analog subcircuits forming a first subset of the set, and a digital subsection coupled to the programmable bias supply to determine the bias currents supplied to the analog subcircuits of the first subset, such that one or more characteristics of the radio integrated circuit are modifiable by programming the programmable bias supply.

Abstract: A wireless local area network system comprises a 5.0+ GHz radio transceiver with two receiving antennas and one transmitting antenna. A transmitter power amplifier output is connected to the transmitting antenna through a 6–8 pole filter to control spurious signal output. Each receiving antenna is fitted with its own low-noise amplifier followed by a simple bandpass filter. Each bandpass filter feeds a diversity switch with a single output to a single receiver. The radio system constitutes a physical-layer (PHY) part of a wireless local-area network.

Abstract: A radio receiver for implementing the physical layer receiving function (PHY) of a wireless data network includes a receive processing pipeline for processing samples of a received packet of data. The samples enter the receive processing pipeline at a first sample rate. A counter generates a running count indicative of the number of samples that have entered the processing pipeline. A comparison unit coupled to the counter determines from the running count if all the samples of the received packet have entered the pipeline. An output of the comparison unit indicates whether or not all samples have entered the pipeline. A clock unit coupled to the comparison unit output provides a clock signal to the pipeline, causing the processing pipeline to process the samples entering the pipeline at a first rate compatible with the first sample rate until the comparison unit output indicates that all samples have entered the pipeline.

Abstract: A wireless computer data network includes several untethered mobile units that make ad-hoc data connections with an Internet-connected base station using the IEEE-802.11a standard. Each unit includes a radio transceiver fully integrated on a single semiconductor chip. The receiver portion is a double-conversion superheterodyne type, and shares the same intermediate and local oscillator frequencies with a two-stage up-conversion transmitter. Two on-chip synthesizers that each include a voltage-controlled oscillator and phase-locked loop can be operated independently for each conversion stage, or operated in offset mode. External reference frequencies can be injected for voltage-controlled oscillator and phase-locked loop testing, chip characterization, and automatic compensation modeling. Each mobile and base unit can be outfitted with transmit/receive antenna transfer switches, RF-power amplifiers, and low-noise receiver amplifiers to increase operating range.

Abstract: A MAC controller for a station in a wireless network, and a method for transmitting packets according to a wireless network MAC protocol. A MAC controller includes a packet scheduler connected to an interface for providing packets for transmission, and transmit hardware connected to a physical layer interface of the station to execute sub-sequences. The transmit hardware includes a buffer to receive from the scheduler and store a set of execution data, and also a signal path to the scheduling engine to provide an indication to the packet scheduler of the outcome of a sub-sequence. The transmit hardware is connected to a receiver to indicate the reception at the wireless station of a data unit that may be a response to a transmission of a sub-sequence.

Abstract: A configurable Viterbi decoder to decode a coded signal for inclusion in a radio receiver for implementing the physical layer receiving function (PHY) of a wireless data network. The decoder includes a branch metric generator with an input to the coded signal, an ACS subsystem coupled to the branch metric generator, and a survivor memory unit coupled to the ACS subsystem. The decoder includes a plurality of outputs each providing a decoded version of the input signal decoded to a distinct decision depth such that the Viterbi decoder is programmable to decode the signal to one of a plurality of decision depths.

Abstract: A phase locked loop (PLL) frequency synthesizer to produce a local oscillator signal for a superheterodyne transmitter for operation at a first and a second RF frequency band that are disparate. The transmitter has a fixed intermediate frequency that is a sizable fraction of the bandwidth of one or more of the RF bands. The superheterodyne transmitter includes a first and a second RF upconverter, each having a local oscillator input coupled to the frequency synthesizer. The synthesizer includes a voltage controlled oscillator (VCO) to provide a VCO frequency signal and a non-integer frequency multiplier to produce a frequency multiplied signal having a frequency wither at the VCO frequency or at a non-integer multiple of the VCO signal depending on a control input.

Abstract: A wireless computer data network includes several untethered mobile units that make ad-hoc data connections with an Internet-connected base station using the IEEE-802.11a standard. Each unit includes a radio transceiver fully integrated on a single semiconductor chip. The receiver portion is a double-conversion superheterodyne type, and shares the same intermediate and local oscillator frequencies with a two-stage up-conversion transmitter. Two on-chip synthesizers that each include a voltage-controlled oscillator and phase-locked loop can be operated independently for each conversion stage, or operated in offset mode. External reference frequencies can be injected for voltage-controlled oscillator and phase-locked loop testing, chip characterization, and automatic compensation modeling. Each mobile and base unit can be outfitted with transmit/receive antenna transfer switches, RF-power amplifiers, and low-noise receiver amplifiers to increase operating range.

Abstract: An apparatus in a node of a wireless network for setting the data rate for sending data to a remote node, and a method for setting the data rate. The method includes receiving a packet from the remote node, determining a measure of signal quality for the received packet; and selecting the data rate for communicating to the remote node according to at least the determined signal quality. The measure of signal quality is a measure of the EVM of the received packet. One implementation conforms to one or more variants of the IEEE 802.11 standard that uses OFDM packets.

Abstract: A frequency synthesizer, a calibrator thereof, and an operating controller thereof are described. The synthesizer comprises a main charge pump that drives a voltage controlled oscillator (VCO) through a loop filter. The calibrator includes a second, replica charge pump that can also drive the VCO, but is set up to output only its maximum or minimum analog output control voltage. Since the construction and characteristics of the replica charge pump duplicate the main charge pump, the main charge pump's minimum and maximum analog control outputs can be cloned out to the VCO on demand. A VCO calibration procedure therefore includes switching the VCO to each of its ranges set by a bank of fixed capacitors, and using the replica charge pump to drive the VCO to its minimum and maximum frequency for each range setting.

Abstract: A converter to convert an N-bit input in a linear scale to an M-bit output in a logarithmic scale. The converter includes a set of K subrange converters each coupled to a respective number of bits of the N-bit input that represents a subrange of the N-bit input, each subrange converter to convert the subrange into a respective output that would be the M-bit output if the most significant set bit in the N-bit input was in the subrange. The converter further includes a range selector having the N-bit input as an input, to indicate which of the subranges to select for an output, and a selector having as inputs the outputs of the subrange converters and coupled to the range selector to select the output of one of the subrange converters as the M-bit output. In one embodiment, the converters operate in parallel.

Abstract: A frequency synthesizer, a calibrator thereof, and an operating controller thereof are described. The synthesizer comprises a main charge pump that drives a voltage controlled oscillator (VCO) through a loop filter. The calibrator includes a second, replica charge pump that can also drive the VCO, but is set up to output only its maximum or minimum analog output control voltage. Since the construction and characteristics of the replica charge pump duplicate the main charge pump, the main charge pump's minimum and maximum analog control outputs can be cloned out to the VCO on demand. A VCO calibration procedure therefore includes switching the VCO to each of its ranges set by a bank of fixed capacitors, and using the replica charge pump to drive the VCO to its minimum and maximum frequency for each range setting.

Abstract: A monolithic transceiver integrated circuit that includes a substrate, a transmitter subsystem of one or more subcircuits on the substrate, and a receiver subsystem of one or more, subcircuits on the substrate. Also included is a bias current supply coupled to the receiver and transmitter subsystems to provide bias current. The bias current supply includes a first bias circuit on the substrate coupled to, and to supply bias current to, a first subcircuit of the transmitter subsystem. The first bias circuit includes a first current modulator having a first switch input to indicate that the bias current is to start or stop being supplied to the first subcircuit. The first current modulator is to control the rate of change of supplied bias current in response to the first switch input. The first subcircuit may be a power amplifier. The control of the rate of change reduces oscillator pull in at least one oscillator included in the integrated circuit.