Patents Assigned to Commissariat a L'Energie
  • Publication number: 20240105872
    Abstract: An interconnector for solar cell strings intended to form a photovoltaic module, the interconnector comprising at least one cell interconnecting strip extending beyond a cell located at the end of the string through an end, and at least one string interconnecting strip, a section of one from among the cell interconnecting strip and the string interconnecting strip has a substantially constant surface, and a variable shape between a first zone of a first thickness and a second zone of a second thickness, the second thickness being strictly less than the first thickness and the second thickness being strictly less than 50 ?m. Each second zone thus constitutes a resistance welding zone without loss in terms of conduction. Without extra thickness at the interconnections, the risk of the module breaking is limited.
    Type: Application
    Filed: December 16, 2021
    Publication date: March 28, 2024
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Yannick ROUJOL, Julien GAUME, Clément JAMIN, Baptiste PERON
  • Publication number: 20240105864
    Abstract: A photodiode including a detection portion made of a first germanium-based crystalline semiconductor material, including a first doped region, a second doped region, and an intermediate region; an interposed portion, in contact with the first doped region, made of a crystalline semiconductor material having a natural lattice parameter equal, to within 1%, to a natural lattice parameter of the first semiconductor material, and a bandgap energy at least 0.5 eV higher than that of the first semiconductor material.
    Type: Application
    Filed: February 9, 2022
    Publication date: March 28, 2024
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Abdelkader ALIANE, Hacile KAYA
  • Patent number: 11942323
    Abstract: A method for forming a doped zone of a transistor includes providing a stack having at least one active layer made from a semiconductor material, and a transistor gate pattern having at least one lateral side, and modifying a portion of the active layer so as to form a modified portion made of a modified semiconductor material. The modified portion extends down to the at least one lateral side of the gate pattern, at the edge of a non-modified portion above which the gate pattern is located. The method also includes forming a spacer on the lateral side, removing the modified portion by selective etching of the modified semiconductor material with respect to the semiconductor material of the non-modified portion, so as to expose an edge of the non-modified portion, and forming the doped zone by epitaxy starting from the exposed edge.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: March 26, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Shay Reboh
  • Patent number: 11937908
    Abstract: A method of performing magnetic resonance imaging of a body includes a) immerging the body in a static and substantially uniform magnetic field; b) exciting nuclear spins inside the body using at least one radio-frequency pulse; c) applying to the body a time-varying magnetic field gradient defining at least one trajectory (ST) in k-space and simultaneously acquiring samples of a magnetic resonance signal so as to perform a pseudo-random sampling (KS) of the k-space; and d) applying a sparsity-promoting nonlinear reconstruction algorithm for reconstructing a magnetic resonance image of the body; wherein, at least in a low-spatial frequency region of the k-space, the distance between any two adjacent points belonging to a same trajectory is lower than 1/FOV, FOV being the size of a field of view of the reconstructed image. A magnetic resonance imaging apparatus for carrying out such a method is also provided.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 26, 2024
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES PARIS, FRANCE, UNIVERSITÉ PARIS-SACLAY, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Nicolas Chauffert, Philippe Ciuciu, Jonas Kahn, Carole Lazarus, Alexandre Vignaud, Pierre Weiss
  • Patent number: 11940825
    Abstract: A voltage divider circuit includes at least two FDSOI transistors (TP1, TP2) of a first type connected to a first supply potential and arranged in a current mirror structure, two FDSOI transistors (TN1, TN2) of a second type and an electrical load (R), the drain of a first—respectively second—transistor (TN1) of the second type being connected to the drain of a first—respectively second—transistor (TP1) of the first type, the drain of the first transistor of the second type being connected to the front-face gate of this same transistor, the front-face gates of the first and second transistors of the second type being connected to one another, the source of the first transistor of the second type being connected to a second supply potential and the load being placed between the source of the second transistor of the second type and the second supply potential.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: March 26, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Anthony Quelen
  • Patent number: 11942328
    Abstract: A method for forming a Bragg reflector includes after forming first trenches in the stack, which are intended to form structures of the distributed Bragg reflector, forming a sacrificial interlayer at least in the first trenches, depositing a second masking layer at least inside the first trenches, forming second trenches intended to form sidewalls of the laser, removing the second masking layer from inside the first trenches, removing said sacrificial interlayer so as to remove, by lift-off, residues of the second masking layer that remain inside the first trenches, and filling said first trenches with at least one metal material.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: March 26, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Maryse Fournier, Vincent Reboud, Jean-Marc Fedeli
  • Patent number: 11941485
    Abstract: A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: March 26, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Louis Hutin, Cyrille Le Royer, François Lefloch, Fabrice Nemouchi, Maud Vinet
  • Patent number: 11944022
    Abstract: A resistive memory cell may be provided with a first electrode and a second electrode arranged on either side of a dielectric layer and facing an interface between a first region and a second region, The first and second region may have different compositions in terms of doping and/or dielectric constant, so as to confine the zone of reversible creation of a conductive filament at the interface.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 26, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Laurent Grenouillet, Marios Barlas, Etienne Nowak
  • Publication number: 20240096668
    Abstract: A method for producing an individualization zone of a microelectronic chip having a first and a second electrical track level, and an interconnection level comprising vias, includes providing the first level and a dielectric layer, forming an etching mask having openings on the dielectric layer, and randomly depositing particles in the openings, by deposition then recirculating the particles on the surface of the etching mask. The dielectric layer is etched through mask openings, so as to obtain functional via openings and degraded via openings. The via openings are filled so as to form the vias of the interconnection level, the vias including functional vias at the functional openings and malfunctional vias at the degraded openings.
    Type: Application
    Filed: May 16, 2023
    Publication date: March 21, 2024
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Stefan LANDIS, Yorrick EXBRAYAT
  • Publication number: 20240096621
    Abstract: A method for crystallising an amorphous layer included in a stack, extending directly in contact with a crystalline layer of the stack by forming an interface with the crystalline layer, and having a first face opposite the interface, and having a melting threshold EM corresponding to the energy density to be provided to the amorphous layer to achieve its melting, for a thickness Ep of the amorphous layer defined between the first face and the interface, the method including a crystallisation annealing of the amorphous layer by subjecting it, by zones, to laser pulses, and in each zone, the laser pulses are emitted by series, each laser pulse having an energy density EDi different from one series to another so as to maintain the energy density of the pulses of each series below the melting threshold.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 21, 2024
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sébastien KERDILES, Pablo ACOSTA ALBA, Angela ALVAREZ ALONSO, Mathieu OPPRECHT
  • Publication number: 20240096898
    Abstract: The present description concerns an electronic device comprising: a silicon layer, an insulating layer in contact with a first surface of the silicon layer, a transistor comprising source, drain, and body regions arranged in the silicon layer, and a gate region topping the body region and comprising a gate portion laterally extending beyond the source and drain regions, the body region being continued by a body contact region not covered with the gate region, and a region of extension of the body region being located under the gate portion; the device further comprising, under the gate portion, a partial insulating trench in the silicon layer extending from a second surface of the silicon layer down to a depth smaller than the thickness of the silicon layer.
    Type: Application
    Filed: March 27, 2023
    Publication date: March 21, 2024
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SAS
    Inventors: Tadeu MOTA FRUTUOSO, Xavier GARROS, Blandine DURIEZ, Sebastien CREMER
  • Publication number: 20240097030
    Abstract: The present description concerns an electronic device comprising: —a silicon layer having a first surface and a second surface, —an insulating layer in contact with the first surface of the silicon layer, —at least one transistor comprising source, drain, and body regions arranged in the silicon layer, and a gate region topping the body region and comprising a gate portion laterally extending beyond the source and drain regions, the body region being continued by a body contact region not covered with the gate region, and a region of extension of the body region being located under the gate portion; the gate portion being less heavily doped than the rest of the gate region.
    Type: Application
    Filed: March 27, 2023
    Publication date: March 21, 2024
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SAS
    Inventors: Sebastien CREMER, Tadeu MOTA FRUTUOSO, Xavier GARROS, Blandine DURIEZ
  • Publication number: 20240097721
    Abstract: An integration system and method for the manufacture of radio frequency transmission front-end modules with radio frequency integrated circuit(s) and self-biased magnetic component(s) integrated on a “Wafer Level Packaging”-type technology. This integration makes it possible to design efficient, compact and low-cost front-end modules.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 21, 2024
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Ayssar SERHAN, Pascal REYNIER, Alexandre GIRY, Perceval COUDRAIN, Jean-Philippe MICHEL
  • Patent number: 11934580
    Abstract: The invention relates to a haptic interface comprising a substrate (2), a plate (4) comprising a surface (6) for interaction with one or more fingers of a user, and actuators (A1) capable of applying a vibration to said plate (4), and a control module (MC) for controlling said actuator,—said plate (4) being in the shape of a strip extending along a first direction (X) and delimited transversely to the first direction by two lateral edges (10), said lateral edges (10) being supported by said substrate (6),—said control module (MC) being configured to generate control signals to said actuator (A1) at first frequencies lower than the cut-off frequency of the first propagation mode of said plate, so that the actuator (A1) generates evanescent waves in the plate (4).
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: March 19, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Ayoub Ben Dhiab, Charles Hudin
  • Patent number: 11936010
    Abstract: A method for detecting an anomaly in operating a battery using a battery management system, including an acoustic receiver attached to a battery wall, and a calculating system connected to the acoustic emitter and the acoustic receiver, a mapping defining a first operating region termed the normal operating region, a second operating region termed the at-risk operating region and a third operating region termed the dangerous operating region, the method including at least one first measurement cycle, each being separated from the preceding measurement cycle by a measurement period, each measurement cycle including receiving an acoustic signal by the acoustic receiver, the received signal being transmitted to the calculating system to obtain a measurement point in the mapping; determining the operating region in which the measurement point is located; and when the measurement point is located in the at-risk operating region or in the dangerous operating region, detecting an anomaly.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: March 19, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Nicolas Guillet
  • Patent number: 11929290
    Abstract: A method is provided for producing a plurality of transistors on a substrate comprising at least two adjacent active areas separated by at least one electrically-isolating area, each transistor of the plurality of transistors including a gate having a silicided portion, and first and second spacers on either side of the gate, the first spacers being located on sides of the gate and the second spacers being located on sides of the first spacers. The method includes forming the gates of the transistors, forming the first spacers, forming the second spacers, siliciding the gates so as to form the silicided portions of the gates, and removing the second spacers. The removal of the second spacers takes place during the silicidation of the gates and before the silicided portions are fully formed.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 12, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Fabrice Nemouchi, Clemens Fitz, Nicolas Posseme
  • Patent number: 11927863
    Abstract: A device for modulating the phase of a light beam includes a matrix of elementary cells, called pixels, coupled to a circuit for addressing the pixels, the device further comprising a set of so-called lateral electrodes extending in a so-called vertical direction (Y) at right angles to the alignment direction (Xa) and configured to apply, for each pixel and via at least two lateral electrodes, a so-called acceleration voltage generating a lateral electrical field (Era) substantially parallel to the alignment direction, in a vector allowing an accelerated return of the liquid crystal molecules to their orientation of rest, the acceleration voltage being configured to be applied in a phase called acceleration relaxation phase, when the activation voltage is no longer applied.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: March 12, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Benoît Racine, Arnaud Verdant, Pierre Joly
  • Patent number: 11929688
    Abstract: A power converter for converting a DC input voltage into an AC output voltage, the power converter having a structure of Phi-2 type, and includes an input terminal for the DC input voltage, an output terminal for the AC output voltage, a power switch equipped with a control electrode, a first electrode and a second electrode linked to a reference potential, the power switch being configured to receive a drive signal at the control electrode, the converter further comprising a self-oscillating circuit, connected between the output terminal and the control electrode, and configured to supply and maintain a sinusoidal drive signal to the power switch from the output voltage.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: March 12, 2024
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INSTITUT POLYTECHNIQUE DE GRENOBLE
    Inventors: Rawad Makhoul, Pierre Perichon, Xavier Maynard, Jia Zhuang, Yves Lembeye
  • Publication number: 20240079548
    Abstract: The present invention pertains to a continuous process for the manufacture of an electrode, to the electrode obtained therefrom and to an electrochemical device comprising said electrode.
    Type: Application
    Filed: December 27, 2021
    Publication date: March 7, 2024
    Applicants: Solvay SA, Commissariat A L'Energie Atomique Et Aux Energies Alternatives
    Inventors: Dominique Bascour, Marc-David Braida, Ludovic Odoni, Julio A Abusleme, Hélène Rouault, Gaëlle Besnard, Léo Merchat, Jérémie Salomon, Benjamin Amestoy
  • Publication number: 20240080202
    Abstract: A method for controlling access of a user equipped with a terminal to a physical or logical resource, the method involving a secure cryptographic device forming a token corresponding to an access criterion, the access token being intended to generate a keystream masking a biometric reference of the user obtained by a biometric reader of the terminal. The biometric reference thus masked is encrypted by fully homomorphic encryption and stored in a database hosted by a remote server. An access control operator obtains a biometric characteristic of the user, homomorphically encrypts it and transmits it to the remote server. This server compares the first and second biometric models in the homomorphic domain and supplies the homomorphically-encrypted result of the comparison to the access control operator. The latter grants or denies access to the user according to the result of the comparison, after having decrypted it.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 7, 2024
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Renaud SIRDEY, Aymen BOUDGUIGA, Martin ZUBER